
dsPIC33/PIC24 Family Reference Manual
DS30009711C-page 10
2006-2019 Microchip Technology Inc.
Figure 4-1:
Structure of Port Shared with PPS Peripherals
I/O TRISx Enable
Q
D
CK
WR LATx/
TRISx Latch
I/O Pin
WR PORTx
Data Bus
Q
D
CK
Data Latch
Read PORTx
Read TRISx
n
0
WR TRISx
Peripheral 2 Output Enable
I/O
Peripheral ‘n’ Output Enable
PIO Module
Output Multiplexers
Output Function
Read LATx
0
1
Peripheral Input
Q
Peripheral 1 Output Enable
0
n
1
1
Peripheral Pin Select
0
n
I/O Pin 0
I/O Pin 1
I/O Pin n
1
Peripheral Input
Pin Selection
Select for the Pin
Peripheral ‘n’ Output Data
Peripheral 2 Output Data
Peripheral 1 Output Data
I/O LATx/PORTx Data
Open-Drain Selection