1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
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10/23/2019
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S
ch
D
oc
Pr
oj
ec
t T
itl
e
PC
B
A
ss
emb
ly
Nu
mb
er:
PC
B
A
R
ev
is
ion
:
Fi
le:
PC
B
N
um
be
r:
P
C
B
R
ev
is
io
n:
De
si
gn
ed
w
it
h
D
ra
w
n
B
y:
PB
Sh
ee
t T
itle
D
eb
ug
ge
r
Engine
er:
A
H
, T
F
A
08-3002
3
S
ize
A
3
A09-
3280
3
Page:
Date
:
A
lt
iu
m
.c
om
D
E
B
U
G
G
E
R
U
S
B
M
IC
R
O
-B
C
O
N
N
E
C
T
O
R
GND
US
BD_P
USBD_N
100n
C1
07
100n
C1
08
RX
TX
U
A
R
T
C
D
C
_
U
A
R
T
1k
R10
7
VCC
_P3V3
S
RST
ST
A
TUS_LED
SHIELD
VBU
S
VCC
_P3V3
GND
TP1
00
Te
st
po
in
t Ar
ray
1
2
3
4
5
6
7
8
9
1
0
TCK
TD
O
TMS
Vsup
TD
I
GN
D
TRST
SRS
T
V
T
ref
GN
D
J102
GN
D
4.
7u
F
C100
D
B
G
0
DBG0
2
1
G
R
E
E
N
L
E
D
SML-
P12MTT86R
D100
V
B
U
S
1
D
-
2
D
+
3
G
N
D
5
S
H
I
E
L
D
1
6
S
H
I
E
L
D
2
7
I
D
4
S
H
I
E
L
D
3
8
S
H
I
E
L
D
4
9
MU-MB0142AB2-269
J105
P
A
D
3
3
P
A
0
0
1
P
A
0
1
2
P
A
0
2
3
P
A
0
3
4
GN
D
10
VD
DA
NA
9
P
A
0
4
5
P
A
0
5
6
P
A
0
6
7
P
A
0
7
8
PA
08
11
PA
09
12
PA
10
13
PA
11
14
PA
14
15
PA
15
16
P
A
1
6
1
7
P
A
1
7
1
8
P
A
1
8
1
9
P
A
1
9
2
0
P
A
2
2
2
1
U
S
B
_
S
O
F
/
P
A
2
3
2
2
U
S
B
_
D
M
/
P
A
2
4
2
3
U
S
B
_
D
P
/
P
A
2
5
2
4
PA
27
25
RE
SE
TN
26
PA
28
27
GN
D
28
VD
DC
OR
E
29
VD
DI
N
30
SW
DC
LK
/P
A3
0
31
SW
DI
O/
PA
31
32
S
AMD21E18A-
MUT
U
100
V
O
U
T
1
V
O
U
T
2
GN
D
3
E
N
4
V
I
N
6
N
C
5
EP
7
MI
C
55
28
-3
.3Y
M
T
U101
VC
C_P3V3
GND
US
BD_P
USBD_N
GND
1u
C1
06
VC
C_MCU_CORE
VC
C_P3V3
VC
C_P3V3
2.
2u
F
C1
01
GND
74
L
VC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U103
V
CC_P3V3
GND
74
L
VC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U
104
VCC_P3V3
G
ND
74
L
VC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U1
05
VCC_P3V3
G
ND
G
ND
G
ND
G
ND
VCC_EDGE
G
ND
74
L
VC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U1
07
VCC_P3V3
G
ND
D
B
G
2
DBG3_CTRL
S1_0_TX
S1_1_R
X
S0_2_TX
DAC
VTG_A
DC
R
E
SE
R
VED
S0_3_C
LK
DB
G0_
CT
RL
CDC_TX
_CTRL
BOOT
D
E
B
U
G
G
E
R
P
O
W
E
R
/S
T
A
T
U
S
L
E
D
E
N
1
B
Y
P
6
V
O
U
T
4
G
N
D
2
V
I
N
3
N
C
/
A
D
J
5
G
N
D
7
MIC5353
U102
100n
C
102
GND
GND
47k
R10
1
27k
R10
4
GND
33k
R
106
2.
2u
F
C
103
GND
1k
R
108
J100
VCC_LEVEL
V
C
C
_R
E
G
U
L
A
T
OR
74
L
VC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U
106
VCC_P3V3
G
ND
D
B
G
1
CDC_RX
CDC_TX
D
B
G
3
DB
G1_
CT
RL
D
E
B
U
G
G
E
R
R
E
G
U
L
A
T
O
R
RE
G_E
NA
BL
E
REG_ENABLE
47k
R10
3
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
47k
R10
2
47k
R10
5
SWCLK
GND
47k
R10
0
GND
DBG2
S
0_0_RX
DBG1_CTRL
DBG0_CTRL
DB
G
3
O
P
E
N
DR
AI
N
T
A
R
G
E
T
A
D
JU
ST
A
B
L
E
R
E
G
U
L
A
T
O
R
SR
ST
D
E
B
U
G
G
E
R
T
E
ST
P
O
IN
T
DB
G2_
CT
RL
VOFF
CDC_RX_CTR
L
47k
R10
9
DBG1
CDC_TX_CTR
L
CDC_RX_CTR
L
SWCLK
RE
G_A
DJU
ST
DB
G2_
GP
IO
DBG3_CTRL
DBG2_CTRL
U
P
DI
U
PDI
G
PIO
G
PIO
RESET
Signa
l
DBG
0
DBG
1
DBG
2
DBG
3
IC
SP
Inter
fa
ce
D
A
T
CLK
G
PIO
MCLR
DBG3
C
D
C
T
X
C
D
C
R
X
U
A
R
T
R
X
U
A
R
T
T
X
U
A
R
T
R
X
U
A
R
T
T
X
T
AR
G
E
T
T
AR
G
E
T
1k
R
110
VB
US
_A
DC
1
2
3
DMN65D8LFB
Q101
VC
C
-
-
I
D
_
S
Y
S
V
O
F
F
1k
R11
2
VCC_P3V3
VT
G_ADC
DAC
MIC94163
V
I
N
B
2
V
O
U
T
A
1
V
I
N
A
2
E
N
C
2
G
N
D
C
1
V
O
U
T
B
1
U108
GND
ID_SYS
VTG_EN
VT
G_E
N
VB
US
_A
DC
SWDI
O
ID_SYS
TP1
01
GND
SWDI
O
VOF
F
47k
R11
1
GND
ID
P
IN
MC36213
F100
VCC_VBUS
VCC_VBUS
VCC_VBUS
J101
V
C
C
_T
ARGET
47k
R
113
P
ro
gr
am
m
in
g
co
nn
ec
to
r
fo
r
fa
ct
or
y
pr
og
ra
m
m
in
g
of
D
E
B
U
G
G
E
R
.
MIC5528:
V
in: 2.5V
to
5
.5
V
V
ou
t:
F
ix
ed
3
.3
V
Im
ax
: 5
00
mA
Dr
opo
ut:
2
60
m
V
@
5
00
m
A
P
T
C
R
es
et
ta
bl
e
fu
se
:
H
ol
d
cu
rr
en
t:
5
00
m
A
T
ri
p
cu
rr
en
t:
1
00
0m
A
A
dj
ust
ab
le
ou
tpu
t a
nd
li
mi
ta
tio
ns
:
-
T
he
D
E
B
U
G
G
E
R
c
an
a
dj
us
t t
he
o
ut
pu
t v
ol
ta
ge
o
f
th
e
re
gu
la
to
r
be
tw
ee
n
1.
25
V
an
d
5.
1V
to
th
e t
ar
ge
t.
-
T
he
v
ol
ta
ge
o
ut
pu
t i
s
li
m
it
ed
b
y
th
e
in
pu
t (
U
S
B
),
w
hi
ch
c
an
v
ar
y
be
tw
ee
n
4.
40
V
to
5
.2
5V
-
T
he
le
ve
l s
hi
ft
er
s
ha
ve
a
m
in
im
al
v
ol
ta
ge
le
ve
l o
f
1.
65
V
an
d
w
il
l l
im
it
th
e
m
in
im
um
o
pe
ra
ti
ng
v
ol
ta
ge
a
ll
ow
ed
f
or
th
e
ta
rg
et
to
s
ti
ll
a
ll
ow
c
om
m
un
ic
at
io
n.
-
T
he
M
IC
94
16
3
ha
s
a
m
in
im
al
v
ol
ta
ge
le
ve
l o
f
1.
70
V
a
nd
w
il
l l
im
it
th
e
m
in
im
um
v
ol
ta
ge
d
el
iv
er
ed
to
th
e
ta
rg
et
.
-
F
ir
m
w
ar
e
co
nf
ig
ur
at
io
n
w
il
l l
im
it
th
e
vo
lt
ag
e
ra
ng
e
to
b
e
w
it
hi
n
th
e
th
e
ta
rg
et
s
pe
ci
fi
ca
ti
on
.
R
11
3
is
r
eq
ui
re
d
to
p
ul
l t
he
Q
10
1
ga
te
to
a
d
ef
in
ed
va
lu
e
w
he
n
th
e
U
10
0
is
n
ot
pow
ered
J100:
C
ut
-s
tr
ap
u
se
d
fo
r
fu
ll
s
ep
ar
at
io
n
of
ta
rg
et
p
ow
er
f
ro
m
th
e
le
ve
l s
hi
ft
er
s
an
d
on
-b
oa
rd
r
eg
ul
at
or
s.
-
Fo
r c
ur
ren
t mea
su
rem
en
ts
us
ing
a
n e
xt
ern
al
po
we
r s
up
ply
, t
hi
s
st
ra
p
co
ul
d
be
c
ut
f
or
m
or
e
ac
cu
ra
te
m
ea
su
re
m
en
ts
. L
ea
ka
ge
b
ac
k
th
ro
ug
h
th
e
sw
it
ch
is
in
th
e
m
ic
ro
a
m
pe
re
r
an
ge
.
J101:
T
hi
s
is
f
oo
tp
ri
nt
f
or
a
1
x2
1
00
m
il
p
it
ch
p
in
-h
ea
de
r
th
at
c
an
b
e
us
ed
f
or
e
as
y
cu
rr
en
t m
ea
su
re
m
en
t
to the
tar
get
m
icr
oc
ont
ro
lle
r
and
the
LE
D /
B
utt
on.
To
u
se
th
e
fo
ot
pr
in
t:
-
C
ut
th
e
tr
ac
k
be
tw
ee
n
th
e
ho
le
s,
a
nd
m
ou
nt
a
p
in
-h
ea
de
r
MIC5353:
V
in: 2.6V
to
6
V
V
out: 1.25V
to
5
.1
V
Im
ax:
5
00
m
A
D
ro
pou
t (
ty
pi
cal
):
50
mV
@
15
0mA
, 16
0mV
@
5
00
m
A
A
cc
ur
ac
y:
2
%
in
it
ia
l
T
he
rm
al
s
hu
td
ow
n
an
d
cu
rr
en
t l
im
it
M
ax
im
um
o
ut
pu
t v
ol
ta
ge
is
li
m
it
ed
b
y
th
e
in
pu
t v
ol
ta
ge
an
d
th
e
dr
op
ou
t v
olt
ag
e
in
the
r
eg
ul
at
or.
(V
m
ax
=
V
in
-
d
ro
po
ut
)
AVR128DA48 Curiosity Nano
Appendix
©
2020 Microchip Technology Inc.
User Guide
DS50002971A-page 30