Here is the address map that is enabled within the sample Xilinx logic design:
Flexbus base address (0x60000000) + offset
Offset
Read Access
Write Access
0x0
SRAM 512K bank
SRAM 512K bank
…
0x0007FFFF
0x0008XXX0
Pin Status GPIO-0 bits 0..7
Output register GPIO-0 bits 0..7
0x0008XXX1
Data direction GPIO-0 bits 0..7 Data direction GPIO-0 bits 0..7
0x0008XXX2
Pin Status GPIO-1 bits 0..7
Output register GPIO-1 bits 0..7
0x0008XXX3
Data direction GPIO-1 bits 0..7 Data direction GPIO-1 bits 0..7
0x0008XXX4
Pin Status GPIO-2 bits 0..7
Output register GPIO-2 bits 0..7
0x0008XXX5
Data direction GPIO-2 bits 0..7 Data direction GPIO-2 bits 0..7
0x0008XXX6
Pin Status GPIO-3 bits 0..7
Output register GPIO-3 bits 0..7
0x0008XXX7
Data direction GPIO-3 bits 0..7 Data direction GPIO-3 bits 0..7
0x0008XXX8
Pin Status GPIO-4 bits 0..7
Output register GPIO-4 bits 0..7
0x0008XXX9
Data direction GPIO-4 bits 0..7 Data direction GPIO-4 bits 0..7
0x0008XXXA
Pin Status GPIO-5 bits 0..7
Output register GPIO-5 bits 0..7
0x0008XXXB
Data direction GPIO-5 bits 0..7 Data direction GPIO-5 bits 0..7
0x0008XXXC Pin Status GPIO-6 bits 0..7
Output register GPIO-6 bits 0..7
0x0008XXXD Data direction GPIO-6 bits 0..7 Data direction GPIO-6 bits 0..7
0x0008XXXE
Pin Status GPIO-7 bits 0..7
Output register GPIO-7 bits 0..7
0x0008XXXF
Data direction GPIO-7 bits 0..7 Data direction GPIO-7 bits 0..7
These registers are mirrored through to offset 0x000BFFFF
The bits in the Data Direction registers when set (=1) specify the relevant GPIO bit as an OUTPUT.
0x000CXXXX SRAM bank select
SRAM bank select
Bits 0 & 1 select which of 4 banks of 512K can be accessed at offset 0x0 by the Flexbus.
00 = Bank 0,
01 = Bank 1,
10 = Bank 2, and
11 = Bank 3.
This register is mirrored throughout the rest of the 1Mbyte address space from 0x000C0000 to
0x000FFFFF.
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