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6I68 Manual 12

CONNECTORS

DIFFERENTIAL PAIRS

The 6I68 supports LVDS signaling on all I/O pairs, that is all even/odd I/O pins

starting with 0 comprise a differential pair on the 6I68. Which FPGA pins can have LVDS
capability depends on the specific daughterboard module.

JTAG CONNECTOR

The 6I68 brings out the 3X2X modules JTAG interface to a 6 pin .1" inline connector

P1. P1 pinout is as follows:

FUNCTION

TMS

TCK

TDI

GND

TDO

2.5V

All manuals and user guides at all-guides.com

Содержание 6i68

Страница 1: ...6I68 3X2X MOTHERBOARD MANUAL Version 1 3 All manuals and user guides at all guides com a l l g u i d e s c o m...

Страница 2: ...This page intentionally not blank All manuals and user guides at all guides com...

Страница 3: ...OSELECT 4 6I68 MODULE PIN CORRESPONDENCE CONNECTORS 5 CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS 5 I O CONNECTOR PIN OUT 6 DIFFERENTIAL PAIRS 12 JTAG PINOUT 12 PCIE PINOUT 12 OPERATION 13 LEDS 1...

Страница 4: ...reaks out the high density daughterboard I O connections into six 50 pin 1 headers with standard AnythingIO pinouts The 6I68 also provides up to 4A of 5V power for I O connectors via an on card switch...

Страница 5: ...tion picture on page 5 EEPROM ENABLE On the 3X20 module the PCI9056 part of the PEX8311 PCIE Local bus bridge chip is configured at power up via a serial EEPROM If the EEPROM is somehow mis programmed...

Страница 6: ...be pulled up to 5V The bus switch input protection function works by disconnecting the FPGA from the IO pins when the IO pin voltage rises above a preset threshold This threshold determines the bus sw...

Страница 7: ...I O voltages Two voltage select pins are provided for each of the banks with selectable voltages W4 W5 LEFT VIO DOWN DOWN 1 5V DOWN UP 1 8V UP DOWN 2 5V UP UP 3 3V W9 W10 RIGHT VIO DOWN DOWN 1 5V DOW...

Страница 8: ...6I68 Manual 5 CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS All manuals and user guides at all guides com...

Страница 9: ...8 7 LEFT VIO IO4 IO14 E7 9 LEFT VIO IO5 IO15 D7 11 LEFT VIO IO6 IO20 D5 13 LEFT VIO IO7 IO21 C5 15 LEFT VIO IO8 IO26 D3 17 LEFT VIO IO9 IO27 D2 19 LEFT VIO IO10 IO32 F4 21 LEFT VIO IO11 IO33 E3 23 LEF...

Страница 10: ...23 A5 15 LEFT VIO IO32 IO28 E4 17 LEFT VIO IO33 IO29 D4 19 LEFT VIO IO34 IO34 F2 21 LEFT VIO IO35 IO35 F3 23 LEFT VIO IO36 IO40 H1 25 LEFT VIO IO37 IO41 H2 27 LEFT VIO IO38 IO46 K1 29 LEFT VIO IO39 IO...

Страница 11: ...VIO IO56 IO24 D1 17 LEFT VIO IO57 IO25 C1 19 LEFT VIO IO58 IO30 E1 21 LEFT VIO IO59 IO31 E2 23 LEFT VIO IO60 IO36 G1 25 LEFT VIO IO61 IO37 G2 27 LEFT VIO IO62 IO42 J4 29 LEFT VIO IO63 IO43 H4 31 LEFT...

Страница 12: ...HT VIO IO80 IO96 L21 17 RIGHT VIO IO81 IO97 L22 19 RIGHT VIO IO82 IO102 K19 21 RIGHT VIO IO83 IO103 K20 23 RIGHT VIO IO84 IO108 H21 25 RIGHT VIO IO85 IO109 H22 27 RIGHT VIO IO86 IO114 E21 29 RIGHT VIO...

Страница 13: ...O IO104 IO98 L19 17 RIGHT VIO IO105 IO99 L20 19 RIGHT VIO IO106 IO104 J21 21 RIGHT VIO IO107 IO105 J22 23 RIGHT VIO IO108 IO110 G21 25 RIGHT VIO IO109 IO111 G22 27 RIGHT VIO IO110 IO116 E19 29 RIGHT V...

Страница 14: ...IO IO128 IO100 K21 17 RIGHT VIO IO129 IO101 K22 19 RIGHT VIO IO130 IO106 J18 21 RIGHT VIO IO131 IO107 J19 23 RIGHT VIO IO132 IO112 F20 25 RIGHT VIO IO133 IO113 F21 27 RIGHT VIO IO134 IO118 D21 29 RIGH...

Страница 15: ...a differential pair on the 6I68 Which FPGA pins can have LVDS capability depends on the specific daughterboard module JTAG CONNECTOR The 6I68 brings out the 3X2X modules JTAG interface to a 6 pin 1 in...

Страница 16: ...d The 5V mode is useful when driving 5V referred loads Note that there is no protection against negative input voltages other than the input clamp diodes in the FPGA and bus switches so negative input...

Страница 17: ...on FPGA Configuration and external load MAX 5V CURRENT TO I O CONNS 300 mA Per Connector MAX 3 3V CURRENT TO I O CONNS 300 mA Per Connector ABSOLUTE MAX I O PIN VOLTAGE 5V 7V 5V tolerant mode ABSOLUTE...