5I25 14
OPERATION
SPI INTERFACE DESCRIPTION
The SPI interface is very minimal, just enough hardware to avoid slow bit banging
of the SPI data when reading or writing the configuration EEPROM. Operation is as
follows: To transfer SPI data, CS is asserted low and an outgoing command/data byte is
written to the data register. This write to the data register causes the SPI interface to clear
its DAV bit, shift out its outgoing data byte, and shift in its incoming data. This shifting is
done at a fixed PCI Clock/6 rate or about 5.5 MHz. When the byte data transfer is done,
The DAV bit is set in the control register. Host software can poll this bit to determine when
the transfer is done. When the transfer is done the incoming data from the EEPROM can
be read in the data register, and the next byte sent out.
Note that CS operation is entirely controlled by the host, that is for example with a
5 byte command sequence, the host must assert CS low, transfer 5 bytes with 5 write/read
commands to the data register with per byte DAV bit polling and finally assert CS high
when done.
FREE EEPROM SPACE
Three 64K byte blocks of EEPROM space are free when both user and fallback
configurations are installed. It is suggested that only the last two blocks, 0xE0000 and
0xF0000 in the user area, be used for FPGA application EEPROM storage.
FALLBACK INDICATION
Mesa’s supplied fallback configurations blink the red INIT LED on the top right hand
side of the card if the primary configuration fails and the fallback configuration loaded
successfully. If this happens it means the user configuration is corrupted or not a proper
configuration for the 5I25s FPGA. This can be fixed by running the configuration utility and
re-writing the user configuration.
FAILURE TO CONFIGURE
The 5I25 should configure its FPGA within a fraction of a second of power
application. If the FPGA card fails to configure, both red LEDs on the right hand side of
the card will remain illuminated after power up. If this happens the 5I25s EEPROM must
be re-programmed via the JTAG connector.
CLOCK SIGNALS
The 5I25 has two FPGA clock signals. One is the PCI clock and the other is a 50
MHz crystal oscillator on the 5I25 card. Both clocks a can be multiplied and divided by the
FPGAs clock generator block to generate a wide range of internal clock signals. Note that
the PCI bus clock is often not known to a high degree of accuracy so for accurate timing
applications, the on card 50 MHz oscillator should be used.
