Mercury KVM266PM, Руководство пользователя

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Using BIOS
CPU & PCI Bus Control
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Scroll to this item and press <Enter> to view the following screen:
Item Help
Menu Level
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Phoenix-AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
PCI1 Master 0 WS Write [Enabled]
PCI2 Master 0 WS Write [Enabled]
PCI1 Post Write [Enabled]
PCI2 Post Write [Enabled]
VLink 8X Support [Enabled]
PCI Delay Transaction [Disabled]
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
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F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
PCI 1/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states, providing faster data
transfer.
PCI 1/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to compensate for the speed
differences between the CPU and PCI bus. When disabled, the writes are not buffered and the
CPU must wait until the write is complete before starting another write cycle.
VLink 8X Support (Enabled)
The item is used to toggle the doubling of the V-Link bus’ clock speed. When set to enabled,
the quad-pumped 8-bit V-Link bus will run at 133MHz, delivering a bandwidth of 533MB/s.
When disabled, the V-Link bus will use a clock speed of 66MHz.
PCI Delay Transaction (Disabled)
The mainboard’s chipset has an embedded 32-bit post write buffer to support delay transac-
tions cycles. Select Enabled to support compliance with PCI specification version 2.1.
Press <Esc> to return to the Advanced Chipset Features screen.
System BIOS Cacheable (Disabled)
When this item is enabled, the System BIOS will be cached for faster execution.
Video RAM Cacheable (Disabled)
When this is enabled, the Video RAM will be cached resulting to better performance.
However, if any program was written to this memory area, this may result to system error.