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Hardware/Software Interface
20G025A00 E3

2017-04-20 Page 61
Table 35. SMBus/IC2 – SATA SGPIO FPGA – Handle State Register (
0xFF
)
Bit Field Description
7 SATA_DETECT Enable or disable passing output pins HANDLE_STATE to the CPU

0: Disable all HANDLE_STATE pins

1: Enable HANDLE_STATE pins
6 SMBALERT_EN Enable or disable passing output interrupt I2C_IRQ_N to the CPU

0: Disable passing SMBALERT interrupt

1: Enable passing SMBALERT interrupt
5 SMBALERT Read access:
SMBALERT interrupt bit

0: SMBALERT interrupt is inactive

1: SMBALERT interrupt is active
Write access:
SMBALERT interrupt acknowledge bit

0: Ignored

1: Acknowledge SMBALERT interrupt
4:0 Reserved
Bit 7 6 5 4 3 2 1 0
Name
HANDLE_
STATE7
HANDLE_
STATE6
HANDLE_
STATE5
HANDLE_
STATE4
HANDLE_
STATE3
HANDLE_
STATE2
HANDLE_
STATE1
HANDLE_
STATE0
Access
R R R R R R R R
Reset
1 1 1 1 1 1 1 1
Bit Field Description
7:0 HANDLE_STATE
[7:0]
Upstream bits from the connected SATA drive

0: SATA drive in slot x connected (handle switch closed)

1: SATA drive in slot x not connected (handle switch open)