Functional Description
MEN Mikro Elektronik GmbH
27
Control Register (
0x70
) (read/write)
There is only one control register for all data elements.
Status Register (
0x60
) (read)
15..8
7..4
3
2
1
0
-
-
IEN IRQ
-
SMP
IEN
Interrupt enable
0= Interrupt disabled
1= Interrupt enabled (default)
If the interrupt is enabled, an interrupt is generated when bit IRQ is reset.
IRQ
This bit is set to 0 every time the internal address pointer points to data
element 0. In order to identify the end of a measuring cycle, this bit must be
set to 1 after the data register has been read.
SMP
Sampling Mode
0 = Internal trigger 123kHz
1 = External trigger <100kHz (t > 10 µs)
If no external clock is available, this bit has to be set to 0.
15..8
7..3
2
1
0
-
-
IRQ BI
-
IRQ
Status of the
IRQ
bit
BI
Present status of the binary input
