Page 14
MD 1772LB (B1770NSL/T)
MEDION
2. Regulation
The DC O/P voltage is proportional to the auxiliary voltage, so I801 pin 2 senses the feedback voltage from
the divider R802, R823, VR801 and R821 to compare with the built-in 2.5 volts reference voltage for error
amplifier operation. Finally pin 6 can modulate the different duty cycle by VR801 setting to achieve
regulation purpose.
4-4-6 Synchronization
1. Normal Mode
The sync pulse from FBT (31 kHz~69 kHz) via C815, R826, D824, C814 and R816 to pin 4 of I801 to
keep I801 synchronized with horizontal sync input frequency.
2. Power Saving Modes: Standby/Suspend
Because there is no pulse from FBT, so the free-run frequency is decided by R816 and C814 and the
SMPS works at 22 kHz.
3. Override
The horizontal free run frequency is about 62.5 kHz under override condition, SMPS is synchronized to
this frequency.
4-4-7 O.V.P.
If the auxiliary voltage is higher than zener voltage ZD807 (18 volts) and makes pin 3 of I801 higher than
1 V, pin 6 duty cycle is limited to have the OVP activated.
4-4-8 O.P.P.
The excess current of T802 through R813, R865 and R864 can develop enough voltage on pin 3 then limit the
power delivered because the pin 6 duty cycle is limited too.
4-4-9 High Voltage Generation with F.B.T.
1. The H. V generation circuit combines T402 F.B.T. with I402 TL494/KA7500 PWM control circuit.
2. When I402, Vcc(pin12) reaches at 5V, pin 5,6 gets a freerun sawtooth waveform about 25KHz, and
approximately 9.5Vp-p, when voltage at pin 15 is higher than pin 16 (5V reference) then release pin 3 to be
controlled by pin 1 feedback signal and compare with pin 5 to output PWM.
3. HFLB1 is used will trigger pin 5 via Q412, to synchronize the deflection circuit.
4. PWM output to drive Q411 and T402 to gererate high voltage (25KV), T402 pin 11, 12 becomes DC/AC
feedback, with the voltage link to I402 non-inverting input pin 1 to stabilize H.V (25KV) and VR401 can be
adjusted to control H.V value.
5. When X.R.P occur, the hunlock will keep high to pull down I402 pin 2 and shut down PWM output.
4-5 Video Amplifier Section
1. RGB signal inputs are terminated by R525, R526 and R527 then pass through the coupling capacitors
C502, C504 and C506 to IC501 TDA 4886 preamplifier.
2. The amplifier RGB signals (0~3 Vpp) are adjusted by I
2
C bus from I501, pin 5 is for clamp pulse which
comes from pin 16 of TDA4856 to set up equal clamp level.
3. The video output stages are amplified by Q963, Q964, Q903, Q904, Q933, Q934, Q962, Q965 Q902,
Q905, Q932, Q935.4. The RGB cathodes cut off are adjusted by VR961, VR901 and VR931.
