LinkIt 2523 HDK v11 User's Guide
© 2015 - 2016 MediaTek Inc.
Page 67 of 82
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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
Figure 46. PERI_SWD
DVDD_VIO_A
CON9002
HE10X2 RA HOUSING
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
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18
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20
R9016
R / 5.1 / K / 0402 / NC
1
2
R9017
R / 0 / ohm / 0402 / NC
1
2
R9018
R / 0 / ohm / 0402 / NC
1
2
R9019
R / 0 / ohm / 0402 / NC
1
2
R9020
R / 0 / ohm / 0402 / NC
1
2
R9021
R / 0 / ohm / 0402 / NC
1
2
CMPDN_J
[10,62]
CMRST_J
[10,62]
CMCSD1_J
[10,62]
CMMCLK_J
[10,62]
CMCSD0_J
[10,62]
Title
Size
Date:
Sheet
of
MediaTek HDK MT2523G
90_DEBUG_IO
C
90
99
Thursday , March 31, 2016
HW trap
R9003
R / 10 / K / 0402 / NC
1
2
R9008
R / 10 / K / 0402
1
2
R9004
R / 10 / K / 0402 / NC
1
2
R9009
R / 10 / K / 0402 / NC
1
2
R9005
R / 10 / K / 0402 / NC
1
2
R9010
R / 10 / K / 0402 / NC
1
2
R9006
R / 10 / K / 0402 / NC
1
2
R9001
R / 10 / K / 0402
1
2
R9002
R / 10 / K / 0402 / NC
1
2
R9007
R / 10 / K / 0402 / NC
1
2
DVDD18_VIO18
VIO28
DVDD_GPO
DVDD18_VIO18
KCOL0
[10,65]
DVDD_GPO
LCM_BLPWM
[10,61]
GPS_HRST_B
[10]
LSCK_LCM
[10,61]
MA_SPI3_B_CS1
[10,63]
MCU JTAG Trapping
The sequence is (GPS_HRST_B, LCM_BLPWM)
Low: Normal mode, High: Test mode
Low: 1.86V, High: 3V
Keep low for image download, keep high for normal boot.
(Low, Low): no JTAG; (Low, High): JTAG at keypad; (High, High): JTAG at CAM
Note 90-1:
Net KCOL0 is the trap pin of USB download.
Note 90-3: This trap pin is used to adjust serial flash voltage.
One of JTAG trap pin, selection combination with note 90-2
Note 90-2:
Schematic design notice of "90_Debug_IO" page.
This trap pin is used to adjust system into system level test or not.
Note 90-4:
Note: 90-1
Note: 90-4
Note: 90-2
Note: 90-3
R9023
R / 0 / ohm / 0402 / NC
1
2
SYSRSTB_IN
[11,66]
