AT INTERFACE DESCRIPTION
5 – 5
Ultra DMA Timing
Ultra DMA Timing
Ultra DMA Timing
Ultra DMA Timing
Ultra DMA Timing
T IM IN G PARAMET ERS
(all tim es in nanoseco nds )
MO DE 0
MO DE 1
MO DE 2
MO DE 3
MO DE 4
MO DE 5
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
CYC
Cycle Time (from STROB E edge to STROBE ed ge)
112
73
54
39
25
16.8
t2
CYC
Two cycle time ( fro m ris ing edge to next r is ing edge or
from falling edge to next fal li ng edge of STROBE )
230
153
115
86
57
38
t
DS
D a ta s etup time (at r ec ipi ent)
15
10
7
7
5
4
t
DH
D ata hold time (at r ec ipi ent)
5
5
5
5
5
4.6
t
DVS
D ata valid setup time at sender (time from data bus bei ng
valid unti l STROB E edge)
70
48
31
20
6.7
4.8
t
DVH
Data valid hold time at sender (time from STRO BE e dge
until data may go invali d)
6.2
6.2
6.2
6.2
6.2
4.8
t
F S
Fi rs t STRO BE (time for devi ce to send fi rst STRO BE)
0
230
0
200
0
170
0
130
0
120
0
90
t
L I
Li mited i nterlock time (time allo wed between an acti on by
one agent, either host or device, and the following acti on
by the othe r agent)
0
150
0
150
0
150
0
100
0
100
0
75
t
ML I
Inter lock ti me wi th mini mum
20
20
20
20
20
20
t
UI
Unli mi ted inte rlock ti me
0
0
0
0
0
0
t
AZ
Maxim um ti me allowed for outputs to r el ease
10
10
10
10
10
10
t
ZAH
Mi nimum delay time re quired for output drivers turni ng on
(from releas ed state )
20
20
20
20
20
20
t
Z AD
0
0
0
0
0
0
t
ENV
Envelope ti me (all control si gnal transi tions are within the
D MACK envelope by thi s much ti me)
20
70
20
70
20
70
20
55
20
55
20
50
t
SR
STROBE to D MA RDY (re sponse ti me to ensure the
synchr onous pause case when the rec ip ient is pausing)
50
30
20
NA
NA
NA
t
RF S
Ready-to-final -STROBE ti me (no more STROBE edges
ma y be sent thi s long after recei ving D MARDY- negati on )
75
70
60
60
60
50
t
RP
Ready-to-p ause ti me (time unti l a reci pient may assume
that the sender has paused after negation of D MARDY-)
160
125
100
100
100
85
t
IORDYZ
Pull-up time before allowing IORD Y to be r eleas ed
20
20
20
20
20
20
t
Z IORD Y
Mi nim um time devi ce shall wait b efor e dr iving IORDY
0
0
0
0
0
0
t
ACK
Setup and hold ti mes before asser ti on and negati on of
DMA C K-
20
20
20
20
20
20
t
SS
Time from STROB E edg e to STOP assertion when the
sender is stopping
50
50
50
50
50
50
DMARQ
(device)
DMACK-
(host)
STOP
(host)
HDMARDY-
(host)
DSTROBE
(device)
DD(15:0)
t
ZAD
DA0, DA1, DA2,
CS0-, CS1-
t
UI
t
ZAD
t
ACK
t
ACK
t
ENV
t
ENV
t
ZIORDY
t
FS
t
FS
t
VDS
t
AZ
t
DVH
t
ACK
Figure 5 - 4
Initiating an Ultra DMA Data In Burst
