AT INTERFACE DESCRIPTION
5 – 2
Pin Description Table
Pin Description Table
Pin Description Table
Pin Description Table
Pin Description Table
P IN NAME
P IN
I/O
S IGNAL NAME
S IGNAL DES C RIP TION
RES ET -
01
I
Hos t Rese t
Rese t si gna l fro m the ho st s yste m. Acti ve d uri ng p o wer up a nd i na cti ve a fter.
D D0
17
I/O
Host Da ta B us
16 b i t b i- dir e ctio na l d a ta bus b e twe e n host a nd d ri ve. L o we r 8 bi ts use d for
r e gi ste r and E C C byte tra nsfe rs. A ll 1 6 bi ts us ed for data tra nsfe rs.
D D1
15
I/O
D D2
13
I/O
D D3
11
I/O
D D4
09
I/O
D D5
07
I/O
D D6
05
I/O
D D7
03
I/O
D D8
04
I/O
D D9
06
I/O
DD 10
08
I/O
D D11
10
I/O
DD 12
12
I/O
DD 13
14
I/O
DD 14
16
I/O
DD 15
18
I/O
D MARQ
21
O
DM A Reque st
Th is si gn al i s used wi th DM AC K fo r D MA tra nsfers . By a sser ti ng thi s s ig nal, the
d ri ve i ndi ca te s tha t d ata i s r e ady to be tr an sfe r ed to a nd from the h ost.
DIOW -
STOP
23
I
Ho st I/O Wr ite
Ri si ng e dge of Wr ite str obe clo ck s d ata from the hos t data b us to a re g i ster o n
the dri ve .
D IOR -
HD MARDY
-
HSTROB E
25
I
Ho st I/O Re ad
Rea d str ob e e na bl es d ata fro m a r e gi ster o n th e dr i ve o nto the ho st d ata b us.
DMA re a dy duri ng Ul tr a DMA d a ta in b ursts.
Da ta stro be d ur i ng UltraDMA data o ut b ursts.
IORDY
DD MARDY
-
DSTROB E
27
O
I/O C ha nne l Rea dy
Thi s si g na l ma y be dr i ven lo w b y the d ri ve to i nse rt wa i t sta te s in to h ost I/O
cycle s.
D MA re a d y dur i ng Ultra DMA da ta o ut b ursts.
D ata str ob e duri ng Ul tr a DMA da ta in b ursts.
CS E L
28
C able S e le ct
Us ed fo r Mas te r/S la ve se lectio n vi a ca bl e. Re q ui res s peci a l cab li ng o n ho st
s yste m a nd i nsta lla tio n of C a bl e Sel ect j ump er.
D MA CK -
29
I
D MA Ackno wled ge
Th is si gn al i s used wi th DM ARQ fo r D MA tra nsfers . By a sser ti ng thi s s ig nal, the
h ost is ac kno wled g i ng the re cei pt of d a ta or i s i nd i cati ng tha t d ata is ava i lable .
INTRQ
31
O
Hos t Inter rup t
Reque st
Inte rru pt to the host a sse rte d whe n the d ri ve req ui re s a tte nti o n fro m the h ost.
IOC S 16
32
D evi ce 1 6 b it I/O
O bso lete
P D IAG -
34
I/O
P as sed D i ag nosti c
Ou tp ut b y d ri ve whe n in Sla ve mod e ; Input to d ri ve whe n i n Maste r mode.
DA0
35
I
Hos t A dd re ss B us
3 b i t bin ar y ad d ress fr om the host to selec t a reg is te r i n the d ri ve .
DA1
33
I
DA2
36
I
C S 0 -
37
I
Ho st Ch ip Se lect 0
C hi p sel ec t fr o m the ho st use d to a ccess the C omm and Bl ock reg i ster s i n the
dr i ve . Thi s si gna l i s a de co de o f I/O ad dr es ses 1 F0 - 1F 7 he x.
C S 1 -
38
I
Ho st Ch ip Se lect 1
Chi p se le ct fro m the host use d to a cce ss the Co ntro l r e gi ste rs in the d ri ve . Thi s
si gna l i s a d e co de of I/O a d dr es ses 3 F6 - 3F 7 hex.
DAS P -
39
I/O
Dr i ve Acti ve /D ri ve
1 P re se nt
Ti me-mul ti p lexed , o p en co lle ctor outp ut whi ch i ndi ca te s tha t a d ri ve i s a ctive , o r
tha t
d e vi ce 1 i s p r es ent.
GND
02
N/A
G round
Si g na l g round.
19
22
24
26
30
40
K EY
20
N/A
K ey
P i n use d fo r ke yi ng the i nterfa ce co nne ctor.