background image

AT INTERFACE DESCRIPTION

5 – 5

Ultra DMA Timing

Ultra DMA Timing

Ultra DMA Timing

Ultra DMA Timing

Ultra DMA Timing

T IM IN G PARAMET ERS

 (all  tim es in nanoseco nds )

MO DE  0

MO DE  1

MO DE  2

MO DE  3

MO DE  4

MO DE  5

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

t

CYC

Cycle Time  (from  STROB E edge to STROBE  ed ge)

112

73

54

39

25

16.8

t2

CYC

Two cycle time ( fro m ris ing edge to  next r is ing edge or
from falling edge  to next fal li ng edge of  STROBE )

230

153

115

86

57

38

t

DS

D a ta s etup  time (at r ec ipi ent)

15

10

7

7

5

4

t

DH

D ata hold time (at r ec ipi ent)

5

5

5

5

5

4.6

t

DVS

D ata valid  setup  time  at  sender  (time from data  bus  bei ng

valid  unti l STROB E  edge)

70

48

31

20

6.7

4.8

t

DVH

Data valid hold time at sender (time from  STRO BE e dge
until data may go invali d)

6.2

6.2

6.2

6.2

6.2

4.8

t

F S

Fi rs t  STRO BE (time for devi ce to send fi rst STRO BE)

0

230

0

200

0

170

0

130

0

120

0

90

t

L I

Li mited i nterlock  time  (time allo wed  between an acti on  by
one agent,  either  host or device, and the following acti on
by  the othe r agent)

0

 150

0

150

0

150

0

100

0

100

0

75

t

ML I

Inter lock ti me  wi th mini mum

20

20

20

20

20

20

t

UI

Unli mi ted  inte rlock  ti me

0

0

0

0

0

0

t

AZ

Maxim um ti me  allowed for  outputs to r el ease

10

10

10

10

10

10

t

ZAH

Mi nimum delay time re quired for  output drivers turni ng on
(from releas ed state )

20

20

20

20

20

20

t

Z AD

0

0

0

0

0

0

t

ENV

Envelope ti me (all control si gnal transi tions are within the
D MACK envelope by thi s much ti me)

20

70

20

70

20

70

20

55

20

55

20

50

t

SR

STROBE to D MA RDY  (re sponse ti me to  ensure the
synchr onous pause case when the rec ip ient is pausing)

50

30

20

NA

NA

NA

t

RF S

Ready-to-final -STROBE ti me  (no more  STROBE edges
ma y be  sent  thi s long after  recei ving  D MARDY-  negati on )

75

70

60

60

60

50

t

RP

Ready-to-p ause ti me (time unti l  a  reci pient may assume

that the sender  has paused after negation of D MARDY-)

160

125

100

100

100

85

t

IORDYZ

Pull-up time before allowing IORD Y to be r eleas ed

20

20

20

20

20

20

t

Z IORD Y

Mi nim um time devi ce shall  wait b efor e  dr iving  IORDY

0

0

0

0

0

0

t

ACK

Setup and  hold ti mes   before asser ti on  and negati on of
DMA C K-

20

20

20

20

20

20

t

SS

Time from STROB E  edg e to  STOP  assertion  when the

sender  is stopping

50

50

50

50

50

50

DMARQ

(device)

DMACK-

(host)

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device)

DD(15:0)

 

t

ZAD

DA0, DA1, DA2,

CS0-, CS1-

t

UI

t

ZAD

t

ACK

t

ACK

t

ENV

t

ENV

t

ZIORDY

t

FS

t

FS

t

VDS

t

AZ

t

DVH

t

ACK

Figure 5 - 4

Initiating an Ultra DMA Data In Burst

Содержание 2R010H1

Страница 1: ...ribed in this publication at any time and without notice Copyright 2001 Maxtor Corporation All rights reserved Maxtor MaxFax and No Quibble Service are registered trademarks of Maxtor Corporation Othe...

Страница 2: ...tic discharge ESD precautions includingpersonnelandequipmentgrounding Stand alonedrivesare sensitive to ESD damage 2 2 2 2 2 BEFORE removing drives from their packing material allow them to reach room...

Страница 3: ...2 2 Read Write Multiple Mode 2 2 Ultra ATA Mode 5 2 2 Multi word DMA EISA Type B Mode 2 2 2 Sector Address Translation 2 2 Logical Block Addressing 2 3 Defect Management Zone 2 3 On the Fly Hardware E...

Страница 4: ...EMC EMI 3 5 EMC Compliance 3 5 Canadian Emissions Statement 3 5 Safety Regulatory Compliance 3 5 Section 4 Section 4 Section 4 Section 4 Section 4 Handling and Installation Handling and Installation H...

Страница 5: ...6 2 Sector Number Register 6 2 Cylinder Number Registers 6 2 Device Head Register 6 2 Status Register 6 2 Command Register 6 3 Read Commands 6 3 Write Commands 6 3 Mode Set Check Commands 6 3 Power Mo...

Страница 6: ...e Immediate 7 8 Standby 7 8 Idle 7 8 Check Power Mode 7 8 Set Sleep Mode 7 8 Default Power on Condition 7 9 Initialization Commands 7 10 Identify Drive 7 10 Initialize Drive Parameters 7 13 Seek Forma...

Страница 7: ...a Transfer to from Device 5 3 5 3 Multi word DMA Data Transfer 5 4 5 4 Initiating an Ultra DMA Data In Burst 5 5 5 5 Sustained Ultra DMA Data In Burst 5 6 5 6 Host Pausing an Ultra DMA Data In Burst 5...

Страница 8: ...puts you in touch with either technical support or customer service We ll provide you the information you need quickly accurately and in the form you prefer a fax a downloaded file or a conversation...

Страница 9: ...ons Signal Conventions Signal Conventions Signal Conventions Signal Conventions Signal names are shown in all uppercase type All signals are either high active or low active signals A dash character a...

Страница 10: ...n allow up to four disks in a 3 5 inch package Key Features Key Features Key Features Key Features Key Features ANSI ATA 5 compliant PIO Mode 5 interface Enhanced IDE Supports Ultra DMA Mode 5 for up...

Страница 11: ...e 2 Multi word DMA EISA Type B Mode 2 Multi word DMA EISA Type B Mode 2 Supports multi word Direct Memory Access DMA EISA Type B mode transfers Sector Address Translation Sector Address Translation Se...

Страница 12: ...mentation Buffer Segmentation Buffer Segmentation Buffer Segmentation The data buffer is organized into two segments the data buffer and the micro controller scratch pad The data buffer is dynamically...

Страница 13: ...ead write heads provides up to eight head selection depending on the model read pre amplification and write drive circuitry Read Write Heads and Media Read Write Heads and Media Read Write Heads and M...

Страница 14: ...accessed via a common interface cable using the same range of I O addresses The drives are jumpered as device 0 or 1 Master Slave and are selected by the drive select bit in the Device Head register...

Страница 15: ...1 Areal Density Gbits in2 max 22 5 Trac k Density tpi 46 000 Recording Density kbpi 391 to 489 Bytes per Sector Block 512 Sectors per Track 572 to 836 Sec tors per Drive 29 297 520 20 011 824 MODELS 2...

Страница 16: ...icalDimensions PhysicalDimensions PhysicalDimensions PhysicalDimensions PhysicalDimensions PARAMETER VALUE Height m ax mm 17 5 Width typical mm 101 6 Length m ax mm 146 6 Weight m ax kg 0 453 Figure3...

Страница 17: ...Sleep Sleep Sleep Sleep Sleep This is the lowest power state with the interface set to inactive A software or hardware reset is required to return the drive to the Standby state EPA Energy Star Compli...

Страница 18: ...dicates the average minimum cycles for reliable load unload function Data Reliability Data Reliability Data Reliability Data Reliability Data Reliability 1 per 10E15 bits read Data errors non recovera...

Страница 19: ...led in a typical personal computer Maxtor recommends that testing and analysis for EMC compliance be performed with the disk mechanism installed within the user s end use application Canadian Emission...

Страница 20: ...baseplate Electro StaticDischarge ESD Electro StaticDischarge ESD Electro StaticDischarge ESD Electro StaticDischarge ESD Electro StaticDischarge ESD To avoid some of the problems associated with ESD...

Страница 21: ...Inspect the shipping container for evidence of damage in transit Notify the carrier immediately in case of damage to the shipping container As they are removed inspect drives for evidence of shipping...

Страница 22: ...ded Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration The Maxtor hard drive design allo...

Страница 23: ...r than 8 4 GB Pentium class processor Operating System Requirements Operating System Requirements Operating System Requirements Operating System Requirements Operating System Requirements Drives less...

Страница 24: ...the Maxtor drive This connector is keyed and will only fit one way Check all other cable connections before you power up Striped colored edge is pin 1 AfterattachingtheIDEinterfacecableandthe powercab...

Страница 25: ...accommodate a cable connection maximum cable length 18 inches Figure5 1 DataConnector PinDescriptionSummary PinDescriptionSummary PinDescriptionSummary PinDescriptionSummary PinDescriptionSummary PIN...

Страница 26: ...to insert wait states into host I O cycles DMA ready during UltraDMA data out bursts Data strobe during UltraDMA data in bursts CSEL 28 Cable Select Used for Master Slave selection via cable Requires...

Страница 27: ...s 30 ns 20 ns t4 DIOW data hold min 30 ns 20 ns 15 ns 10 ns 10 ns t5 DIOR data setup min 50 ns 35 ns 20 ns 20 ns 20 ns t6 DIOW data hold min 5 ns 5 ns 5 ns 5 ns 5 ns t6Z DIOR data tristate max 30 ns 3...

Страница 28: ...ld min 5 ns 5 ns 5 ns tG DIOR DIOW data setup min 100 ns 30 ns 20 ns tH DIOW data hold min 20 ns 15 ns 10 ns tI DMACK to DIOR DIOW setup min 0 0 0 tJ DIOR DIOW to DMACK hold min 20 ns 5 ns 5 ns tKr DI...

Страница 29: ...UI Unlimited interlock time 0 0 0 0 0 0 tAZ Maximum time allowed for outputs to release 10 10 10 10 10 10 tZAH Minimum delay time required for output drivers turning on from released state 20 20 20 20...

Страница 30: ...tDVH DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host tDVH tCYC tCYC tDVS tDVS tDH tDS tDH tDS t2CYC tDH tDVH t2CYC DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD...

Страница 31: ...DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tACK tACK tZAH tDVH tSS tLI Figure5 7 DeviceTerminatinganUltraDMADataInBurst tDVH CRC tAZ DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0...

Страница 32: ...5 0 at device tDVH tCYC tCYC tDVS tDVS tDS tDH t2CYC tDH tDVH t2CYC DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tLI tDVS tDVH t...

Страница 33: ...BE host DD 15 0 host tSR tRFS tRP Figure5 11 DevicePausinganUltraDMADataOutBurst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI t...

Страница 34: ...TION 5 10 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tMLI tDVS tLI tLI tACK CRC tDVH tACK tIORDYZ tMLI tRP tRFS Figure5 13 DeviceTerminatinganU...

Страница 35: ...egister A read only register containing specific information regarding the previous command Data interpretation differs depending on whether the controller is in operational or diagnostic mode A power...

Страница 36: ...elect LBA Mode Enabling this bit for commands not supported by LBA mode will abort the selected command When set the Task File register contents are defined as follows for the Read Write and translate...

Страница 37: ...ng retries disabled Write Verify Sector s 3Ch Write Sector Buffer E8h Write Multiple C5h Write DMA CAh CBh No retries ModeSet CheckCommands ModeSet CheckCommands ModeSet CheckCommands ModeSet CheckCom...

Страница 38: ...F o r m at T ra ck 0 1 0 1 0 0 0 0 N N N Y Y S e e k 0 1 1 1 x x x x N N Y Y Y E xecu te D iag no sti c 1 0 0 1 0 0 0 0 N N N N D Initia li ze P a ra m e ter s 1 0 0 1 0 0 0 1 N Y N N Y R ea d S e cto...

Страница 39: ...s the drive in the reset state Clearing the bit re enables the drive The software Reset bit must be held active for a minimum of 5 sec IRQ Enable Setting the Interrupt Request Enable to 0 enables the...

Страница 40: ...The Busy bit does not clear until the reset clears and the drive completes initialization Completion of a reset operation does not generate a host interrupt Task File registers are initialized as fol...

Страница 41: ...Commands WriteCommands WriteCommands Write Sector s Write Verify Sector s Write Sector Buffer Write DMA Multi word DMA Ultra DMA Write Multiple ModeSet CheckCommands ModeSet CheckCommands ModeSet Chec...

Страница 42: ...egisters contain the numbers of the cylinder head and sector of the last sector read Back to back sector read commands set DRQ and generate an interrupt when the sector buffer is filled at the complet...

Страница 43: ...cution is also similar to that of the READ SECTOR S command except that 1 Several sectors are transferred to the host as a block without intervening interrupts 2 DRQ qualification of the transfer is r...

Страница 44: ...tor number of the last sector written The next time the buffer is ready to be filled during back to back Write Sector commands DRQ is set and an interrupt is generated After the host fills the buffer...

Страница 45: ...Multiple commands report after the attempted disk write of the block or partial block in which the error occurred The write operation ends with the sector in error even if it was in the middle of a b...

Страница 46: ...03h Set Transfer Mode based on value in Sector Count register 05h Enable Advanced Power Management 42h Enable Automatic Acoustic Management The sector count register contains the Automatic Ac oustic M...

Страница 47: ...Lock Set Max Lock Set Max Lock Set Max Lock After this sub command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK are rejected The drive remains in this state un...

Страница 48: ...he Automatic Power Down sequence Idle 97h E3h Idle 97h E3h Idle 97h E3h Idle 97h E3h Idle 97h E3h Spin up and change time out value This command will spin up the spin motor if the drive is spun down I...

Страница 49: ...the value placed in the Sector Count register is multiplied by five seconds to obtain the Time out Interval value If no drive commands are received from the host within the Time out Interval the drive...

Страница 50: ...14 8 retired 7 1 removable media device 6 1 not removable controller and or device 5 3 retired 2 response incomplete 1 retired 0 reserved 1 Number of logical cylinders 2 Reserved 3 Number of logical...

Страница 51: ...DMA transfer modes supported 64 15 8 reserved 7 0 advanced PIO transfer modes supported 65 Minimum multi word DMA transfer cycle time per word 15 0 cycle time in nanoseconds 66 Manufacturer s recommed...

Страница 52: ...ted If words 82 and 83 0000h or FFFFh command set notification not supported 15 10 as c urrently defined 9 1 Automatic Acoustic Management feature set supported 8 0 as currently defined 88 Ultra DMA 1...

Страница 53: ...the number of logical cylinders Upon receipt of the command the drive 1 Sets BSY 2 Saves the parameters 3 Resets BSY and 4 Generates an interrupt To specify maximum heads write 1 less than the maximum...

Страница 54: ...is full the drive resets DRQ sets BSY and begins command execution If the drive is not already on the desired track an implied seek is performed Once at the desired track the data fields are written...

Страница 55: ...codes are D0h S M A R T Read Attribute Value This feature returns 512 bytes of attribute information to the host D1h S M A R T Read Attribute Thresholds This feature returns 512 bytes of warranty fail...

Страница 56: ...Maxtor s No Quibble Service policy By minimizing paperwork and processing No Quibble Service dramatically cuts the turnaround time normally required for repairs and returns Here s how it works 1 Custo...

Страница 57: ...one phone to listen to technical information about Maxtor products and the top Q A s from our 24 hour automated voice system Continental USA 800 2MAXTOR 800 262 9867 Press 1 wait for announcement list...

Страница 58: ...ess time The average time to make all possible length accesses seeks average seek time The average time to make all possible length seeks A typical measure of performance B B B B B bad block A block t...

Страница 59: ...simultaneously under the set of read write heads This three dimensional storage volume can be accessed after a single seek cylinder zero The outermost cylinder in a drive that can be used for data st...

Страница 60: ...ection code ECC A mathematical algorithm that can detect and correct errors in a data field This is accomplished with the aid of Check Bits added to the raw data error free A recording surface that ha...

Страница 61: ...ference Used to update the physical disk address tracks and sectors of files and to expedite accesses inside diameter The smallest radial position used for the recording and playback of flux reversals...

Страница 62: ...rocessor It is usually but not necessarily desktop size microprocessor A central processing unit CPU manufactured as a chip or a small number of chips missing pulse A term used in surface certificatio...

Страница 63: ...re performed by the host processor using PIO register accesses to the data register plated thin film media Magnetic disk memory media having its surface plated with a thin coating of a metallic alloy...

Страница 64: ...read write head on track can be either open loop quasi closed loop or closed loop servo track A track on a servo surface The prerecorded reference track on the dedicated servo surface of a disk drive...

Страница 65: ...in question with or without repositioning the head V V V V V voice coil motor A positioning motor that uses the same principle as a voice coil in a loudspeaker The motor has no detent positions The me...

Отзывы: