DS5001FP
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Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this
configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system
with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The
bidirectional byte-wide data bus connects the data I/O lines of the SRAM.
Figure 5. CONNECTION TO 128k x 8 SRAM
Содержание DS5001FP
Страница 3: ...DS5001FP 3 of 26 Figure 1 BLOCK DIAGRAM ...
Страница 8: ...DS5001FP 8 of 26 Figure 4 MEMORY MAP WITH PES 1 ...
Страница 14: ...DS5001FP 14 of 26 EXPANDED PROGRAM MEMORY READ CYCLE EXPANDED DATA MEMORY READ CYCLE ...
Страница 15: ...DS5001FP 15 of 26 EXPANDED DATA MEMORY WRITE CYCLE ...
Страница 22: ...DS5001FP 22 of 26 RPC TIMING MODE ...
Страница 25: ...DS5001FP 25 of 26 44 PIN MQFP ...
