Maxim DS5001FP Скачать руководство пользователя страница 15 | Manualshive

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DS5001FP

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EXPANDED DATA-MEMORY WRITE CYCLE

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Содержание DS5001FP

Страница 1: ...cision bandgap reference for power monitor Fully 8051 compatible 128kB scratchpad RAM Two timer counters On chip serial port 32 parallel I O port pins Software security available with DS5002FP secure microprocessor PIN ASSIGNMENT Top View P0 4AD4 CE2 PE2 BA9 P0 3 AD3 BA8 P0 2 AD2 BA13 P0 1 AD1 R W P0 0 AD0 VCC0 VCC MSEL P1 0 BA14 P1 1 BA12 P1 2 BA7 P1 3 PE3 PE4 BA6 P2 6 A14 CE3 CE4 BD3 P2 5 A13 BD...

Страница 2: ...er selectable program and data segments This partition can be selected at program loading time but can then be modified later at any time The microprocessor decodes memory access to the SRAM and addresses memory through its byte wide bus Memory portions designated code or ROM are automatically write protected by the microprocessor Combining program and data storage in one device saves board space ...

Страница 3: ...DS5001FP 3 of 26 Figure 1 BLOCK DIAGRAM ...

Страница 4: ... to invoke the bootstrap loader At this time PSEN is pulled down externally This should only be done once the DS5001FP is already in a reset state The device that pulls down should be open drain since it must not interfere with PSEN under normal operation 34 6 RST Active High Reset Input A logic 1 applied to this pin will activate a reset state This pin is pulled down internally so this pin can be...

Страница 5: ...falls below VLI Connect PE1 to battery backed functions only 3 N A PE2 Peripheral Enable 2 Accesses data memory between addresses 4000h and 7FFFh when the PES bit is set to a logic 1 PE2 is lithium backed and remains at a logic high when VCC falls below VLI Connect PE2 to battery backed functions only 22 N A PE3 Peripheral Enable 3 Accesses data memory between addresses 8000h and BFFFh when the PE...

Страница 6: ...ZATION Figure 2 illustrates the memory map accessed by the DS5001FP The entire 64k of program and 64k of data are potentially available to the byte wide bus This preserves the I O ports for application use The user controls the portion of memory that is actually mapped to the byte wide bus by selecting the program range and data range Any area not mapped into the NV RAM is reached by the expanded ...

Страница 7: ...DS5001FP 7 of 26 Figure 3 MEMORY MAP IN PARTITIONABLE MODE PM 0 Note Partitionable mode is not supported when MSEL pin 0 128kB mode ...

Страница 8: ...DS5001FP 8 of 26 Figure 4 MEMORY MAP WITH PES 1 ...

Страница 9: ... in this configuration both program and data are stored in a common RAM chip Figure 6 shows a similar system with using two 32kB SRAMs The byte wide address bus connects to the SRAM address lines The bidirectional byte wide data bus connects the data I O lines of the SRAM Figure 5 CONNECTION TO 128k x 8 SRAM ...

Страница 10: ...coded chip enables and the R W signal go to an inactive logic 1 state VCC is still the power source at this time When VCC drops further to below VLI internal circuitry switches to the lithium cell for power The majority of internal circuits are disabled and the remaining nonvolatile states are retained Any devices connected VCCO are powered by the lithium cell at this time VCCO is at the lithium b...

Страница 11: ... 0V and VLI 0V In this state the contents of SRAM are not battery backed and are undefined DC CHARACTERISTICS TA 0 C to 70 C VCC 5V 10 PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Low Voltage VIL 0 3 0 8 V 1 Input High Voltage VIH1 2 0 VCC 0 3 V 1 Input High Voltage RST XTAL1 PROG VIH2 3 5 VCC 0 3 V 1 Output Low Voltage at IOL 1 6mA Ports 1 2 3 PF VOL1 0 15 0 45 V 1 11 Output Low Voltage at IOL ...

Страница 12: ... Lithium Supply Voltage VLI 2 5 4 0 V 1 Operating Current at 16MHz ICC 36 mA 2 Idle Mode Current at 12MHz 0 C to 70 C IIDLE 7 0 mA 3 Idle Mode Current at 12MHz 40 C to 85 C IIDLE 8 0 mA 3 10 Stop Mode Current ISTOP 80 µA 4 Pin Capacitance CIN 10 pF 5 Output Supply Voltage VCCO VCCO1 VCC 0 45 V 1 2 Output Supply Battery Backed Mode VCCO CE 1 4 PE 1 2 0 C to 70 C VCCO2 VLI 0 65 V 1 8 Output Supply B...

Страница 13: ... tPSAV tCLK 8 ns 12 Address Valid to Valid Instruction In at 12MHz at 16MHz tAVVI 5tCLK 150 5tCLK 90 ns ns 13 PSEN Low to Address Float tPSLAZ 0 ns 14 RD Pulse Width tRDPW 6tCLK 100 ns 15 WR Pulse Width tWRPW 6tCLK 100 ns 16 RD Low to Valid Data In at 12MHz at 16MHz tRDLDV 5tCLK 165 5tCLK 105 ns ns 17 Data Hold After RD High tRDHDV 0 ns 18 Data Float After RD High tRDHDZ 2tCLK 70 ns 19 ALE Low to ...

Страница 14: ...DS5001FP 14 of 26 EXPANDED PROGRAM MEMORY READ CYCLE EXPANDED DATA MEMORY READ CYCLE ...

Страница 15: ...DS5001FP 15 of 26 EXPANDED DATA MEMORY WRITE CYCLE ...

Страница 16: ...RAMETER SYMBOL MIN MAX UNITS 28 External Clock High Time at 12MHz at 16MHz tCLKHPW 20 15 ns 29 External Clock Low Time at 12MHz at 16MHz tCLKLPW 20 15 ns 30 External Clock Rise Time at 12MHz at 16MHz tCLKR 20 15 ns 31 External Clock Fall Time at 12MHz at 16MHz tCLKF 20 15 ns EXTERNAL CLOCK TIMING ...

Страница 17: ...ERISTICS continued POWER CYCLE TIME TA 0 C to 70 C VCC 5V 10 PARAMETER SYMBOL MIN MAX UNITS 32 Slew Rate from VCCMIN to VLI tF 130 µs 33 Crystal Startup Time tCSU Note 9 34 Power On Reset Delay tPOR 21 504 tCLK POWER CYCLE TIMING ...

Страница 18: ...X UNITS 35 Serial Port Clock Cycle Time tSPCLK 12tCLK µs 36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK 133 ns 37 Output Data Hold After Rising Clock Edge tCHDO 2tCLK 117 ns 38 Clock Rising Edge to Input Data Valid tCHDV 10tCLK 133 ns 39 Input Data Hold After Rising Clock Edge tCHDIV 0 ns SERIAL PORT TIMING MODE 0 ...

Страница 19: ...uring Op Code Fetch tCE1HOV 0 ns 45 Byte Wide Address Hold After CE 1 4 PE 1 4 or CE1N High During MOVX tCEHDA 4tCLK 30 ns 46 Delay from Byte Wide Address Valid CE 1 4 PE 1 4 or CE1N Low During MOVX tCELDA 4tCLK 35 ns 47 Byte Wide Data Setup to CE 1 4 PE 1 4 or CE1N High During MOVX read tDACEH 1tCLK 40 ns 48 Byte Wide Data Hold After CE 1 4 PE 1 4 or CE1N High During MOVX read tCEHDV 0 ns 49 Byte...

Страница 20: ...B READ TA 0 C to 70 C VCC 5V 10 PARAMETER SYMBOL MIN MAX UNITS 54 CS A0 Setup to RD tAR 0 ns 55 CS A0 Hold After RD tRA 0 ns 56 RD Pulse Width tRR 160 ns 57 CS A0 to Data Out Delay tAD 130 ns 58 RD to Data Out Delay tRD 0 130 ns 59 RD to Data Float Delay tRDZ 85 ns ...

Страница 21: ...63 Data Setup to WR tDW 130 ns 64 Data Hold After WR tWD 20 ns AC CHARACTERISTICS DMA TA 0 C to 70 C VCC 5V 10 PARAMETER SYMBOL MIN MAX UNITS 65 DACK to WR or RD tACC 0 ns 66 RD or WR to DACK tCAC 0 ns 67 DACK to Data Valid tACD 0 130 ns 68 RD or WR to DRQ Cleared tCRQ 110 ns AC CHARACTERISTICS PROG TA 0 C to 70 C VCC 5V 10 PARAMETER SYMBOL MIN MAX UNITS 69 PROG Low to Active tPRA 48 CLKS 70 PROG ...

Страница 22: ...DS5001FP 22 of 26 RPC TIMING MODE ...

Страница 23: ...nnected RST MSEL XTAL1 VSS 5 Pin capacitance is measured with a test frequency 1MHz TA 25 C 6 ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation 7 ILI is the current drawn from VLI input when VCC 0V and VCCO is disconnected 8 VCCO2 is measured with VCC VLI and a maximum load of 10µA on VCCO 9 Crystal startup time is the time required to get the mass of t...

Страница 24: ...DS5001FP 24 of 26 80 PIN MQFP MM DIM MIN MAX A 3 40 A1 0 25 A2 2 55 2 87 B 0 30 0 50 C 0 13 0 23 D 23 70 24 10 D1 19 90 20 10 E 17 70 18 10 E1 13 90 14 10 e 0 80 BSC L 0 65 0 95 56 G4005 001 ...

Страница 25: ...DS5001FP 25 of 26 44 PIN MQFP ...

Страница 26: ...1 PF signal moved from VOL2 test specification to VOL1 PCN No D72502 2 AC characteristics for battery backed SDI pulse specification added The following represent the key differences between 061297 and 051099 version of the DS5001FP data sheet Please review this summary carefully 1 Reduced absolute maximum voltage to VCC 0 5V 2 Added note clarifying storage temperature specification is for non bat...

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