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Applications Information

IF Filter Center Frequency Configuration

The FCEN bits in the Configuration 1 register are used

to set the center frequency of the IF filter when it is

configured as a bandpass filter. The following equations

are used to calculate the required setting of FCEN to obtain

the target center frequency. The center frequency should

not be set higher than 9MHz for any filter bandwidth.
For FBW = 000 corresponding to a 2.5MHz filter bandwidth,

the center frequency is calculated using the following equation:

CENTER

128 - FCEN

0.195M Hz













For FBW = 010 corresponding to a 4.2MHz filter bandwidth,

the center frequency is calculated using the following equation:

CENTER

128 - FCEN

0.355M Hz













For FBW = 001 corresponding to a 8.7MHz filter

bandwidth, the center frequency is calculated using the

following equation:

CENTER

128 - FCEN

0.66M Hz













Here are some examples: If FBW = 000, and FCEN[6:0]

= 1011000, then the 2.5MHz wide filter will be centered at

approximately [(128 – 88)/2](0.195) MHz = 3.9MHz.
If FBW = 001, and FCEN = 1101001, then the 8.7MHz

wide filter will be centered at approximately
[(128 – 105)/2](0.66) MHz = 7.6MHz.
The calculations give approximate center frequencies.

The center frequency needs to be tuned empirically.

Operation for Wideband Signals

Some signals used for precision GNSS or modernized

GNSS have wide bandwidths. For example, the GPS L1

P(Y) signal has a main lobe (first null spacing) of 20.46

MHz, and the Galileo E6 signal is 10.23 MHz wide. For

such wideband signals, the use of the wideband lowpass

filter is recommended so as to fit the entire main lobe of

the signal within the passband of the filter and by doing

so, avoid reducing the SNR.
First, the LO frequency has to be tuned to the center of

the wanted signal so as to down-convert the signal to

DC. For the case of the GPS L1 P(Y) signal, the required

LO frequency is 1575.42MHz. As an example, assume

the TXCO frequency is 16.368 MHz. Assume the PLL

reference division ratio (RDIV) = 16 giving a comparision

frequency of 1.023 MHz. This allows use of the Integer-N

PLL. Set the INT_PLL bit in the PLL Configuration register

to 1. The PLL integer division ratio (NDIV) needs to be set

to 1575.42/1.023 = 1540.
The IF filter is configured as a low pass 5

-order

Butterworth 23.4MHz filter. Configure FBW = 011, F3OR5

= 0, and FCENX = 0. The FCEN bits can be left

untouched since they are ignored for the lowpass filter

case. Set the filter pole at the mixer output to 36MHz by

setting MIXPOLE = 1. The ADC sampling rate should

be set to a few MHz beyond the double-sided passband

of the IF filter which is 23.4MHz in this case. This is to

avoid degradation due to aliasing of noise. The offset

frequency (from the 3dB corner frequency) at which the

attenuation is 20dB is 18.5MHz. Hence, an ADC sampling

rate of at least two times this, or 37MHz, is required.

With a 16.368MHz TCXO clock, it is not possible, given

the limitations on fractional division ratio and maximum

frequency of the clock multiplier, to generate a 37MHz

clock internally. The ADC clock is, therefore, provided

from an external source on the ADC_CLKIN pin and the

EXTADCLK register bit set to use the externally applied

ADC clock.
As a second example, assume reception of the Galileo

E5a signal is desired. This has a bandwidth of 20.46MHz

and is centered at a frequency of 1176.45MHz. Since this

frequency is in the L2/L5 band, the LOBAND bit in the

PLL Configuration register must be set to 1. Assuming

the same TXCO and reference division ratios as in the

prior example, this means the integer division ratio must

be 1150. Again, since the center frequency is an integer

multiple of 1.023MHz, the PLL can be operated as an

Integer-N PLL. (The use of a 1.023MHz comparison

frequency is convenient since most GNSS carrier frequencies

will be integer multiples of 1.023MHz.) Since this is also a

20.46MHz wide signal, the IF filter settings and ADC clock

configuration are the same as the prior example.
For a final example, consider reception of the Galileo

E1 signal. This is 14.3MHz wide and centered at

the frequency of 1575.42MHz. Assuming the same

conditions as the prior examples, the synthesizer will be

programmed identically to the first example. The IF filter

will be programmed identically to the first example except

for the bandwidth. The 16.4MHz wide filter setting should

be used instead (FBW = 111). An ADC sampling rate of

at least 26MHz is required. In this case, it is decided to

simply multiply the TXCO clock by 2 giving an ADC clock

frequency of 32.7MHz.

www.maximintegrated.com

Maxim Integrated

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MAX2771

Multiband Universal GNSS Receiver

Содержание MAX2771

Страница 1: ...chip ADCs can be bypassed and the analog I and Q signals output for sampling with external ADCs An analog monitoring feature is provided that allows simultaneous output of the on chip ADC samples and the I analog signal The MAX2771 is packaged in a 5mm x 5mm 28 pin TQFN package with an exposed paddle Applications Location Enabled Mobile Handsets PNDs Personal Navigation Devices Telematics Asset Tr...

Страница 2: ...LANOUT_HI VCCCP I0 VCCRF LNA LNA FILTER SPI PLL VCO 90 0 MIXIN_HI NC LD CLKOUT XTAL I1 Q0 Q1 VCCADC SHDN CSN CPOUT VCCVCO ADC_CLKIN VCCD SDATA SCLK MIXIN_LO LNAOUT_LO LNAIN_LO VCCIF ANAINOUT ANAIPOUT ADC ADC MAX2771 www maximintegrated com Maxim Integrated 2 MAX2771 Multiband Universal GNSS Receiver ...

Страница 3: ...ifier LNA 17 Mixer 17 Synthesizer 18 IF Filter 18 Programmable Gain Amplifier PGA 19 Automatic Gain Control AGC 19 ADC 20 ADC Fractional Clock Divider 22 ADC Clock Alignment 22 DSP Interface 22 Reference Clock 24 Serial Interface 25 Register Map 28 Register Details 31 Configuration 1 0x0 31 Configuration 2 0x1 33 Configuration 3 0x2 35 PLL Configuration 0x3 37 PLL Integer Division Ratio 0x4 39 PLL...

Страница 4: ...on Circuit 48 Circuit 1 48 External Component List 49 Ordering Information 49 Revision History 50 Figure 1 ADC Quantization Levels for 2 and 3 Bit Cases 21 Figure 2 DSP Interface Top Level Connectivity and Control Signals 23 Figure 3 Clock Distribution 24 Figure 4 Register Read Functional Timing 26 Figure 5 Register Write Functional Timing 26 Figure 6 Three Wire Interface Timing Diagram 27 TABLE O...

Страница 5: ...n Reference Settings 19 Table 12 Output Data Format 20 Table 9 ADC Output Data Format Settings 20 Table 10 IQ Channels Enable Settings 20 Table 11 ADC Output Bits Setting 20 Table 13 Frequency of ADC Sampling Clock vs Reference Clock 22 Table 14 Reference Divider Settings 25 Table 15 Serial Interface Timing Requirements 27 Table 16 External Component List 49 LIST OF TABLES www maximintegrated com ...

Страница 6: ...ve Note 2 27 Idle ModeTM IDLE bit is 1 SHDN high 5 Shutdown mode SHDN low 200 μA Digital Input Logic High VIH Measure at the SHDN pin 1 5 V Digital Input Logic Low VIL Measure at SHDN pin 0 4 V Package Code T2855 8 Outline Number 21 0140 Land Pattern Number 90 0023 Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These ar...

Страница 7: ...rd Order Input Intercept Point L2 L5 Band L2 L5 band Note 6 Measured at the low band mixer input Note 4 9 dBm In Band Mixer Input Referred 1dB Compression Point Measured at the high band mixer input 85 dBm In Band Mixer Input Referred 1dB Compression Point L2 L5 Band L2 L5 band Note 6 Measured at the low band mixer input 85 dBm Mixer Input Return Loss Measured at high band mixer input 10 dB Mixer ...

Страница 8: ...z FBW 111 single sided BW Note 7 8 2 FBW 100 single sided BW Note 7 18 Stopband Attenuation 3rd order filter bandwidth 2 5MHz measured at 4MHz offset Note 7 30 dB 5th order filter bandwidth 2 5MHz measured at 4MHz offset Note 7 50 Passband Flatness FBW 001 Filter center frequency 8 9MHz 5th order BPF response magnitude at 5 1MHz response magnitude at 11 6MHz Note 7 3 dB AC ELECTRICAL CHARACTERISTI...

Страница 9: ...iven from a 50Ω source All RF measurements are done in the analog output mode with ADC bypassed PGA gain is set to GAININ 111010 through SPI interface unless otherwise noted Maximum IF output load is not to exceed 10kΩ 7 5pF on each pin Typical values are at VCC 2 85V and TA 25 C unless otherwise noted Note 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS FREQUENCY SYN...

Страница 10: ...ENCY toc04 S12 S21 50 40 30 20 10 0 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 2 1 2 2 LOW BAND LNA INPUT RETURN LOSS dB FREQUENCY MHz LOW BANDLNA INPUT RETURN LOSS vs FREQUENCY toc07 30 25 20 15 10 5 0 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 2 1 2 2 HIGH BAND LNA OUTPUT RETURN LOSS dB FREQUENCY MHz HIGH BAND LNAOUTPUT RETURN LOSS vs FREQUENCY toc02 0 0 2 0 4 0 6 0 8 1 1 2 1 4 17 17 5 18 18 5 19 19 5...

Страница 11: ...CY FBW 000 toc10 FCEN 1011000 50 40 30 20 10 0 10 0 2 4 6 8 10 12 14 16 18 20 MAGNITUDE dB BASEBANDFREQUENCY MHz 3RD ORDER POLYPHASE FILTER RESPONSE vs BASEBAND FREQUENCY FBW 001 toc13 FCEN 1101001 50 40 30 20 10 0 10 0 2 4 6 8 10 12 14 16 18 20 MAGNITUDE dB BASEBAND FREQUENCY MHz 5TH ORDER LOW PASS FILTER RESPONSE vs BASEBAND FREQUENCY FBW 011 toc16 50 40 30 20 10 0 10 0 2 4 6 8 10 12 14 MAGNITUD...

Страница 12: ...0 10 0 3 6 9 12 15 MAGNITUDE dB BASEBANDFREQUENCY MHz 5TH ORDER LOW PASS FILTERRESPONSE vs BASEBAND FREQUENCY FBW 111 toc20 0 0 5 1 1 5 2 2 5 95 100 105 110 115 120 40 15 10 35 60 85 HIGH BAND NOISE FIGURE dB HIGH BAND CASCADED GAIN dB TEMPERATURE C HIGH BAND CASCADED GAIN AND NOISE FIGURE vs TEMPERATURE toc23 NOISE FIGURE GAIN 40 50 60 70 80 90 100 110 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 ...

Страница 13: ...10 15 20 25 30 35 40 45 50 55 60 65 HIGH BAND NOISE FIGURE MIXER INPUT dB PGA GAIN CODE HIGH BAND NOISE FIGURE MIXER INPUT vs PGA GAIN CODE toc25 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 30 35 40 45 50 55 60 65 LOW BAND MIXER INPUT REFERRED GAIN dB PGA GAIN CODE LOW BANDMIXER INPUT REFERRED GAIN vs PGA GAIN CODE toc29 TA 85 C TA 25ºC TA 40ºC 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 50...

Страница 14: ... to ground with a 100nF capacitor as close as possible to the pin Power 7 SDATA Data Signal of 3 Wire Serial Interface Digital Input Output 8 SCLK Clock Input of 3 Wire Serial Interface Serial data is clocked in on the rising edge of the SCLK and output on the falling edge of SCLK Digital Input 9 CSN Chip Select Input of 3 Wire Serial Interface Set CSN low to select device Set CS high when the SPI...

Страница 15: ...CMOS Logic Output A logic high indicates the PLL is locked Digital output 18 SHDN Operation Control Logic Input A logic low shuts off the entire device Digital input 19 LNAIN_HI High Band LNA Input Port Requires external matching circuit of 5 6nH series inductor and 1 7pF shunt capacitor Analog input 20 LNAIN_LO Low Band LNA Input Port Requires external matching circuit of 8 4nH series inductor an...

Страница 16: ...I LD I0 LNA LNA FILTER SPI PLL VCO 90 0 MIXIN_HI CLKOUT XTAL I1 Q0 Q1 CSN CPOUT SDATA SCLK MIXIN_LO LNAOUT_LO LNAIN_LO ANAINOUT ANAIPOUT ADC ADC MAX2771 www maximintegrated com Maxim Integrated 16 MAX2771 Multiband Universal GNSS Receiver ...

Страница 17: ...output low IF or zero IF I and Q signals There are two inputs to the mixer one for high band and the other for low band The high band mixer input impedance is matched to 50Ω at a frequency of 1575MHz while the low band mixer input impedance is matched to 50Ω at a frequency of 1227MHz The quadrature mixer requires a low side LO injection The output of the LNA and the input of the mixer are brought ...

Страница 18: ...ng the TCXO frequency fTCXO by the PLL reference division ratio RDIV For example let the TCXO frequency be 20MHz RDIV be 1 and the nominal LO frequency be 1575 42MHz The following method can be used when calculating divider ratios supporting various reference and comparison frequencies TCXO COMP f 20MHz f 20MHz RDIV 1 LO COMP f 1575 42MHz LO_Frequency_Divider 78 771 f 20MHz Integer Divider 78 d 00...

Страница 19: ...selection of visible satellites which in turn allows faster time to fix and a more accurate navigation solution Programmable Gain Amplifier PGA The MAX2771 integrates a baseband programmable gain amplifier that provides typically 59dB of gain control range The PGA gain can either be controlled autono mously by the MAX2771 using the AGC function or be directly controlled by the host through program...

Страница 20: ... BITS field in the Configuration 2 register See Table 11 Figure 1 illustrates the ADC quantization levels for 2 bit and 3 bit cases and also describes the sign magnitude data mapping The variable T 1 designates the location of the magnitude threshold for the 2 bit case Also refer to Table 12 The maximum ADC sampling rate is 44MHz Table 9 ADC Output Data Format Settings Table 10 IQ Channels Enable ...

Страница 21: ...1 ADC Quantization Levels for 2 and 3 Bit Cases 1 2 3 4 5 6 7 1 2 3 4 5 6 7 000 001 010 011 01 00 100 101 110 111 10 11 T 1 www maximintegrated com Maxim Integrated 21 MAX2771 Multiband Universal GNSS Receiver ...

Страница 22: ...clock will be taken from the ADC_CLKIN pin instead of using the internally generated clock In a multiple MAX2771 scenario all devices are assumed to be running off the same TCXO clock One device would be designated as the clock source and configured to output its ADC clock on its CLKOUT pin This clock signal can then be buffered and distributed through an external clock tree The buffered clocks ar...

Страница 23: ...e beginning of each valid 16 bit data slice In addition there is a TIME_SYNC signal that is output every 128 to 16 384 cycles of the ADC clock Given that the serial clock has to run multiple times faster than the ADC clock the use of the DSP interface is limited to narrowband signals that don t require a high ADC sampling clock frequency Figure 2 DSP Interface Top Level Connectivity and Control Si...

Страница 24: ...by the REFCLK bits in the PLL Configuration Register Refer to Table 14 This table ignores the fractional ratio The maximum frequency of the pre divided reference clock is 22MHz if the x2 option is selected and 11MHz if the x4 option is selected The ADC sampling clock can then be generated by a second fractional divider This is described in the section on the ADC The CLKOUT signal to the baseband c...

Страница 25: ... drive SDATA for the remainder of the transaction The 14th through 16th bits are turnaround bits that are denoted TA The purpose of these bits is to allow time for the bus to change direction in the case of a read and so avoid any possible contention for the bus In the case of a read transaction the host releases SDATA during this interval and the MAX2771 does not yet start driving SDATA In the ca...

Страница 26: ...n output the host tri states SDATA and subsequently brings CSN high completing the transaction If the host does not assert CSN the MAX2771 will ignore any activity on SCLK or SDATA This allows multiple MAX2771 devices to be connected to the SPI and controlled by one host Only the MAX2771 that has its CSN input asserted will react to the host Figure 6 illustrates the timing relationships between th...

Страница 27: ...lling edge to SDATA tri stated 25 ns tDZA SCLK falling edge to SDATA active 25 ns tCSH Last SCLK rising edge to rising edge of CSN 10 ns tDP SCLK falling edge to data out propagation delay 25 ns tCSNOFF CSN rising edge to next SPI transaction CSN falling edge 100 ns Figure 6 Three Wire Interface Timing Diagram SCLK CSN SDATA tDS tCP tCSS tCSH tDH tDAZ tDZA tDP tCSNOFF www maximintegrated com Maxim...

Страница 28: ...DIEID 1 0 0x02 Configuration 3 31 24 RESERVED 3 0 GAININ 5 2 Configuration 3 23 16 GAININ 1 0 RE SERVED HILOAD EN RE SERVED RE SERVED RE SERVED RE SERVED Configuration 3 15 8 FHIPEN RE SERVED PGAIEN PGA QEN STR MEN STRM START STRM STOP RE SERVED 2 Configuration 3 7 0 RESERVED 1 0 STRMBITS 1 0 STAM PEN TIME SYN CEN DATA SYN CEN STR MRST 0x03 PLL Configuration 31 24 REFDIV 2 0 LOBAND RE SERVED RE SE...

Страница 29: ... 0 RESERVED 27 24 RESERVED 23 16 RESERVED 23 16 RESERVED 15 8 RESERVED 15 8 RESERVED 7 0 RESERVED 7 0 0x07 Clock Configuration 1 31 24 RESERVED 2 0 EXTA DCCLK REFCLK_L_CNT 11 8 Clock Configuration 1 23 16 REFCLK_L_CNT 7 0 Clock Configuration 1 15 8 REFCLK_M_CNT 11 4 Clock Configuration 1 7 0 REFCLK_M_CNT 3 0 FCLKIN ADCCLK RE SERVED MODE 0x08 Test Mode 1 31 24 RE SERVED RE SERVED RESERVED 1 0 RESER...

Страница 30: ...RESERVED 4 0 Test Mode 2 7 0 RESERVED 4 0 RE SERVED RE SERVED RE SERVED 0x0A Clock Configuration 2 31 24 RESERVED 2 0 RE SERVED ADCCLK_L_CNT 11 8 Clock Configuration 2 23 16 ADCCLK_L_CNT 7 0 Clock Configuration 2 15 8 ADCCLK_M_CNT 11 4 Clock Configuration 2 7 0 ADCCLK_M_CNT 3 0 PRE FRAC DIV_SEL CLK OUT_ SEL RESERVED 1 0 Register Map continued www maximintegrated com Maxim Integrated 30 MAX2771 Mul...

Страница 31: ...58 0x0 0x0 0x1 0x1 Access Type Write Read Write Read Write Read Write Read Write Read BITFIELD BITS DESCRIPTION DECODE CHIPEN 31 Chip enable Set to 1 to enable the chip and 0 to disable the chip except for the serial bus 0x0 Disable chip 0x1 Enable chip IDLE 30 Idle enable 0x0 Operating mode 0x1 Idle mode RESERVED 29 26 Reserved Write 1111 to this bitfield RESERVED RESERVED 25 22 Reserved Write 10...

Страница 32: ...efer to Applications section for details on usage FBW 5 3 IF filter bandwidth selection 0x0 2 5 MHz 0x1 8 7 MHz 0x2 4 2 MHz 0x3 23 4 MHz lowpass mode only 0x4 36 0 MHz lowpass mode only 0x5 RESERVED 0x6 RESERVED 0x7 16 4 MHz lowpass mode only F3OR5 2 Filter order selection 0x0 5th order filter 0x1 3rd order filter FCENX 1 Polyphase filter selection 0x0 Lowpass filter 0x1 Complex bandpass filter FG...

Страница 33: ...0x0 0x0 Access Type Write Read Write Read Write Read Write Read Read Only BITFIELD BITS DESCRIPTION DECODE RESERVED 31 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 30 29 Reserved DO NOT CHANGE VALUE RESERVED ANAIMON 28 Enables continuous spectrum monitoring by routing analog I outputs to pins 0x0 Monitoring disabled 0x1 Monitoring enabled IQEN 27 I and Q channels enable 0x0 I channel only enable...

Страница 34: ...r of bits in the ADC 0x0 1 bit 0x1 Reserved 0x2 2 bits 0x3 Reserved 0x4 3 bits 0x5 Reserved 0x6 Reserved 0x7 Reserved DRVCFG 5 4 output driver configuration 0x0 CMOS logic 0x1 Reserved 0x2 Analog outputs ADC bypass mode 0x3 Analog outputs ADC bypass mode RESERVED 3 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 2 Reserved DO NOT CHANGE VALUE RESERVED DIEID 1 0 Identifies version of IC Configuratio...

Страница 35: ... 0 STAMPEN TIME SYNCEN DATA SYNCEN STRMRST Reset 0x7 0x1 0x1 0x1 0x0 0x0 Access Type Write Read Write Read Write Read Write Read Write Read Write Read BITFIELD BITS DESCRIPTION DECODE RESERVED 31 28 Reserved DO NOT CHANGE VALUE RESERVED GAININ 27 22 PGA gain value programming in steps of ap proximately 1dB per LSB RESERVED 21 Reserved DO NOT CHANGE VALUE RESERVED HILOADEN 20 Enable output driver t...

Страница 36: ...Number of bits streamed 0x0 Reserved 0x1 I MSB I LSB 0x2 Reserved 0x3 I MSB I LSB Q MSB Q LSB STAMPEN 3 Enables the insertion of the frame number at the beginning of each frame If disabled only the ADC data is streamed to the output 0x0 Disable frame number insertion 0x1 Enable frame number insertion TIME SYNCEN 2 Enables the output of the time sync pulses at all times when streaming is enabled by...

Страница 37: ...5 4 3 2 1 0 Field RESERVED RESERVED 2 0 INT_PLL PWRSAV RESERVED RESERVED Reset 0x0 0x0 0x1 0x0 0x0 0x0 Access Type Write Read Write Read Write Read Write Read Write Read Write Read BITFIELD BITS DESCRIPTION DECODE REFDIV 31 29 Clock output divider ratio 0x0 XTAL frequency x2 0x1 XTAL frequency 4 0x2 XTAL frequency 2 0x3 XTAL frequency 0x4 XTAL frequency x4 0x5 Reserved 0x6 Reserved 0x7 Reserved LO...

Страница 38: ...CHANGE VALUE RESERVED ICP 9 Charge pump current selection 0x0 0 5 mA 0x1 1 mA RESERVED 8 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 7 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 6 4 Reserved DO NOT CHANGE VALUE RESERVED INT_PLL 3 PLL mode control Selects either integer N or fractional N PLL mode 0x0 Fractional N PLL 0x1 Integer N PLL PWRSAV 2 Enable PLL power save mode 0x0 Disable PLL power...

Страница 39: ...13 12 11 10 9 8 Field NDIV 2 0 RDIV 9 5 Reset 1536 16 Access Type Write Read Write Read BIT 7 6 5 4 3 2 1 0 Field RDIV 4 0 RESERVED 2 0 Reset 16 0x0 Access Type Write Read Write Read BITFIELD BITS DESCRIPTION DECODE RESERVED 31 28 Reserved DO NOT CHANGE VALUE RESERVED NDIV 27 13 PLL integer division ratio RDIV 12 3 PLL reference division ratio RESERVED 2 0 Reserved DO NOT CHANGE VALUE RESERVED www...

Страница 40: ... RESERVED RESERVED RESERVED RESERVED Reset 0x7 0x0 0x0 0x0 0x0 Access Type Write Read Dual Write Read Write Read Write Read Write Read BITFIELD BITS DESCRIPTION DECODE RESERVED 31 28 Reserved DO NOT CHANGE VALUE RESERVED FDIV 27 8 PLL fractional division ratio RESERVED 7 4 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 3 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 2 Reserved DO NOT CHANGE VALUE...

Страница 41: ...Access Type Write Read BIT 15 14 13 12 11 10 9 8 Field RESERVED 15 8 Reset 0x8000000 Access Type Write Read BIT 7 6 5 4 3 2 1 0 Field RESERVED 7 0 Reset 0x8000000 Access Type Write Read BITFIELD BITS DESCRIPTION DECODE RESERVED 31 28 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 27 0 Reserved DO NOT CHANGE VALUE RESERVED www maximintegrated com Maxim Integrated 41 MAX2771 Multiband Universal GNSS...

Страница 42: ...DE RESERVED 31 29 Reserved DO NOT CHANGE VALUE RESERVED EXTADCCLK 28 Selects either internally generated or exter nally applied clock as ADC sampling clock 0x0 Use internally generated clock 0x1 Use clock provided on ADC_CLKIN pin REFCLK_ L_CNT 27 16 Sets the value for the L counter REFCLK_ M_CNT 15 4 Sets the value for the M counter FCLKIN 3 Fractional clock divider selection 0x0 Bypass ADC clock...

Страница 43: ...ESCRIPTION DECODE RESERVED 31 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 30 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 29 28 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 27 24 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 23 20 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 19 16 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 15 12 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 11 Reser...

Страница 44: ...T CHANGE VALUE RESERVED RESERVED 30 Reserved DO NOT CHANGE VALUE RESERVED RD_CALC 29 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 28 25 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 24 22 Reserved Write 011 to this bitfield RESERVED RESERVED 21 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 20 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 19 18 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 17...

Страница 45: ...0x0 0x0 0x0 Access Type Write Read Write Read Write Read Write Read BITFIELD BITS DESCRIPTION DECODE RESERVED 31 29 Reserved DO NOT CHANGE VALUE RESERVED RESERVED 28 Reserved DO NOT CHANGE VALUE RESERVED ADCCLK_ L_CNT 27 16 Sets the value for the L counter ADCCLK_ M_CNT 15 4 Sets the value for the M counter PRE FRACDIV_ SEL 3 Fractional clock divider selection 0x0 Bypass fractional clock divider 0...

Страница 46: ...filter is configured as a low pass 5th order Butterworth 23 4MHz filter Configure FBW 011 F3OR5 0 and FCENX 0 The FCEN bits can be left untouched since they are ignored for the lowpass filter case Set the filter pole at the mixer output to 36MHz by setting MIXPOLE 1 The ADC sampling rate should be set to a few MHz beyond the double sided passband of the IF filter which is 23 4MHz in this case This...

Страница 47: ...est performance take into consideration grounding and routing of RF baseband and power supply lines Make connections from vias to the ground plane as short as possible On the high impedance ports keep traces short to minimize shunt capacitance EV kit Gerber files are available on the MAX2771 product page of the Maxim Integrated website Power Supply Layout To minimize coupling between different sec...

Страница 48: ...OUT XTAL I0 Q0 Q1 VCCADC SHDN CSN CPOUT VCCVCO ADC_CLKIN VCCD SDATA SCLK MIXIN_LO LNAOUT_LO LNAIN_LO VCCIF ANAINOUT ANAIPOUT C14 C13 C12 C11 C10 C9 C8 C7 C4 C6 C5 R0 C0 C1 C2 C3 REFERENCE CLOCK OUTPUT REFERENCE CLOCK INPUT C15 L0 C16 L1 MAX2771 Circuit 1 Typical Application Circuit www maximintegrated com Maxim Integrated 48 MAX2771 Multiband Universal GNSS Receiver ...

Страница 49: ... coupling capacitor C14 1 0 1nF supply voltage bypass capacitor R0 1 15kΩ PLL loop filter resistor L0 1 5 6 nH RF matching inductor for high band LNA inputs L1 1 8 4 nH RF matching inductor for low band LNA input C15 1 1 7 pF RF matching capacitor for high band LNA input C16 1 1 1 pF RF matching capacitor for low band LNA input Table 16 External Component List Denotes a lead Pb free RoHS compliant...

Страница 50: ...ifications without notice at any time The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed Other parametric values quoted in this data sheet are provided for guidance Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products Inc 2018 Maxim Integrated Products Inc 50 MAX2771 Multiband Universal GNSS Receiver For prici...

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