Maxim Integrated MAX20335, Руководство пользователя

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Table 35. PwrCmd Register (0x1F)
Table 34. PwrCfg Register (0x1E)
ADDRESS: 0x1E
MODE: Read/Write
BIT 7 6 5 4 3 2 1 0
NAME
PFNx
ResEna
– – – – – – StayOn
PFNxResEna
PFN_ PFNx Automatic Internal Pull-Up/Pull-Down Enable
0 = No internal pullup/pulldown
1 = Automatic i nternal pullup/pulldown as per Table 1
StayOn
This bit is used to ensure that the processor booted correctly. This bit must be set within 5s of power-on to
prevent the part from shutting down and returning to the power-off condition. This bit has no effect after being
set.
0 = Shut down 5s after power-on
1 = Stay on
ADDRESS: 0x1 F
MODE: Read/Write
BIT 7 6 5 4 3 2 1 0
NAME
PWR_CMD[ 7 :0]
PWR_CMD
[ 7 :0]
Power Command Register
Writing the following values issues the command listed:
0xB2 = places the part in off mode
0xC3 = issues a hard reset (power cycle)
0xD4 = issues a soft reset (reset pulse only)
After the written value has been validated by the internal logic, this register is cleared automatically. Any other
commands will be ignored.
See Table 1 for the available PwrCmd for each PwrRstCfg value.
MAX20335 PMIC with Ultra-Low I
Q
Voltage Regulators and
Battery Chargers for Small Lithium Ion Systems
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