34
DRAM Clock/Drive Control
Scroll to this item and press <Enter> to view the following screen:
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
Item Help
Current FSB Frequency
Current DRAM Frequency
DRAM Clock
[By SPD]
DRAM Timing
[Auto by SPD]
DRAM CAS Latency
[2.5]
Bank Interleave
[Disabled]
Precharge to Active (Trp)
[3T]
Active to Precharge (Tras)
[6T]
Active to CMD (Trcd)
[3T]
DRAM Burst Length
[4]
DRAM Queue Depth
[4 level]
DRAM Command Rate
[2T Command]
Menu Level
↑
↓
→
←
: Move
Enter : Select
+/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
Current FSB Frequency
This item displays the frontside bus (FSB) frequency. This is a display-only
item. You cannot make changes to this field.
Current DRAM Frequency
This item displays the memory (DRAM) frequency. This is a display-only item.
You cannot make changes to this field.
DRAM Clock (By SPD)
This item enables you to manually set the DRAM Clock. We recommend that
you leave this item at the default value.
DRAM Timing (Auto by SPD)
Set this By SPD to enable the system to automatically set the SDRAM timing
by SPD (Serial Presence Detect). SPD is an EEPROM chip on the DIMM
module that stores information about the memory chips it contains, including
size, speed, voltage, row and column addresses, and manufacturer. If you
disable this item, you can use the following three items to manually set the
timing parameters for the system memory
DRAM CAS Latency (2.5)
Enables you to select the CAS latency time in HCLKs of 2/2 or 3/3. The value
is set at the factory depending on the DRAM installed. Do not change the va l-
ues in this field unless you change specifications of the installed DRAM or the
installed CPU. The options are "2" and "2.5" default.
Bank Interleave (Disabled)
Enable this item to increase memory speed. When enabled, separate memory
banks are set for odd and even addresses and the next byte of memory can
be accessed while the current byte is being refreshed.
