MOP-TFT480272-43A-BLM-TPC
8
9
AC Characteristics
9.1
Pixel Timing
Figure 3:Pixel Timing
Input Output Timing
DLCK clock time
Tclk
33.3
-
-
ns
DCLK = 30MHZ
DCLK clock low period
Tcwl
40
-
60
%
DLCK clock high period
Tcwh
40
-
60
%
Clock rising time
Trck
9
-
-
ns
Clock falling time
Tfck
9
-
-
ns
HSD width
Thwh
1
-
-
DCLK
HSD period time
Th
55
60
65
μs
HSD setup time
Thsu
12
-
-
ns
HSD hold time
Thhd
12
-
-
ns
VSD width
Tvwh
1
-
-
Th
VSD setup time
Tvsu
12
-
-
ns
VSD hold time
Tvhd
12
-
-
ns
Data setup time
Tdasu
12
-
-
ns
Data hold time
Tdahd
12
-
-
ns
DE setup time
Tdesu
12
-
ns
DE hold time
Tdehd
12
-
-
ns
Time from VSD to 1
st
line
data input
Tvs
3
8
31
TH
HV mode By HDL[4:0]
setting
