Marvin Test Solutions GX5280, Руководство пользователя

Страница: 13 / 50

Chapter 2 - Overview 5
GX5280 Architecture and Capabilities
The following are key GX5280 characteristics and architecture:

The GX5280 is a Plug and Play (PnP) board. The operating system (Windows 9x, Me, Windows 2000 or XP)
automatically identify and arbitrate resource requirements as well as notify the user that a new board was found
and automatically install the driver for it.

DIO domain operates independently of the host computer when in RUN mode.

Each GX5280 DIO board supports a maximum clock frequency of up to 200MHz (GX5283 Only) per channel
for all channels.

A GX5280 (Master) board controls the timing of its domain and can be synchronized to a UUT.

Any GX5280 board can be transforms to be Master or Slave depends on the on-board switch settings (can only
be done when the system is shutdown)

Multiple Master boards are used to synchronize mutually asynchronous UUT elements.

Each GX5280 Slave board adds 32 UUT channels. Up to 15 Slave boards can be added to make a total of 512
channel domain.

Programmable channel’s output enabled or disabled. Each channel can be enabled or disabled at any time
through software control. Disabled channels in output mode are in Tri-State. This is useful for connecting to a
user bus

Each Master has a 16-bit external event bus. This bus is used for triggering and synchronization with external
events.

Multiple trigger sources are available: Programmed PXI Trigger line, Star Trigger, External Trigger, Internal
trigger (software) or event driven trigger (generated by external events). All triggers sources can work in
tandem.

Event driven trigger can be generated by external events on the Timing connector External Event lines. Event
and Mask registers are used to determine both the triggering event and the masking bits to be ignored. These use
the D Event and D Mask registers and T Event and T Mask registers.

External triggering can be initiated on sequential or concurrent events by using both D and T event registers to
define events.

Multiple pause sources are available: Programmed PXI Trigger line, External Pause, Internal pause (software)
or event driven pause (generated by external events). All pause sources can work in tandem.

The test sequence (vector) can be paused on external events unconditionally or conditionally. P Event and P
Mask registers hold the condition and bits that generate a conditional pause.

An X Register is used to emulate an External Event condition under program control for purposes of test
program verification. The register is loaded through the computer bus.

DIO domain can be set to have internal or external clock, in order to synchronize with the user UUT.

DIO domain clock source (internal or external), active when outputting data, can be programmatically delayed
by 0-24 nSec (increments of 4nSec).

DIO domain Strobe source (internal or external), active when inputting data, can be programmatically delayed
by 0-24 nSec (increments of 4nSec).

All GX5280 Firmware can be upgraded through the DIO In-System- Programming (ISP).

Direction can be programmed on a per byte basis, i.e. Group 0 (channels 0 -7) can be set as output while Group
1 (channels 8 -15) can be set to be input etc.