ES9010K2M (MAIN : IC52)
PIN Functions
R
ES
E
TB
D
AT
A
_C
LK
D
AT
A1
D
AT
A2
G
P
IO
1
N
.C
.
N
.C
.
28 27 26 25 24 23 22
DGND
D
1
2
1
VDD
D
N
G
D
0
2
2
.
C
.
N
.
C
.
N
9
1
3
L
C
S
A
C
C
V
8
1
4
A
D
S
G
E
R
V
7
1
5
R
D
D
A
E
R
V
6
1
6
O
X
F
XI (
.
C
.
N
5
1
7
)
K
L
C
M
8 9 10 11 12 13 14
N
.C
.
D
A
C
R
D
AC
R
B
N
.C
.
A
G
N
D
D
A
C
L
D
AC
LB
ES9010K2M
28-QFN
PIN DESCRIPTIONS
Pin
Name
Pin Type
Reset
State
Pin Description
1
DGND
Ground
Ground
Digital Ground
2
N.C.
-
-
No internal connection. Pin may be grounded if desired.
3
SCL
I
Tri-stated
I
2
C Serial Clock Input
4
SDA
I/O
Tri-stated
I
2
C Serial Data Input/Output
5
ADDR
I
Tri-stated
I
2
C Address Select
6
XO
AO
Floating
XTAL Out
7
XI (MCLK)
AI
Floating
XTAL / MCLK In
8
N.C.
-
-
No internal connection. Pin may be grounded if desired.
9
DACR
AO
Driven to
ground
Differential Positive Analog Output Right
10
DACRB
AO
Driven to
ground
Differential Negative Analog Output Right
11
N.C.
-
No internal connection. Pin may be grounded if desired.
12
AGND
Ground
Ground
Analog Ground
13
DACL
AO
Driven to
ground
Differential Positive Analog Output Left
14
DACLB
AO
Driven to
ground
Differential Negative Analog Output Left
15
N.C.
-
-
No internal connection. Pin may be grounded if desired.
16
VREF
-
-
Reference Voltage (Decoupling)
17
VREG
Power
Power
Analog supply from internal regulator (Decoupling)
18
VCCA
Power
Power
1.8V to +3.3V
19
N.C.
-
-
No internal connection. Pin may be grounded if desired.
20
DGND
Ground
Ground
Digital Ground
21
DVDD
Power
(Internal /
External)
Power
Digital Core Voltage
This is internally generated by a regulator from DVCC.
DVDD needs to be externally supplied for high XI / MCLK
frequency. Please refer to the section about DVDD supply on p.8.
22
N.C.
-
-
No internal connection. Pin may be grounded if desired.
23
N.C.
-
-
No internal connection. Pin may be grounded if desired.
24
GPIO1
I/O
Tri-stated
GPIO 1
25
DATA2
I
Tri-stated
DSD Data2 (R) OR PCM Data CH1/CH2 or SPDIF Input 2
26
DATA1
I/O
Tri-stated
Master mode off: Input for DSD Data1 (L) OR PCM Frame Clock
or SPDIF Input 3
Master mode on: Output for PCM Frame Clock
27
DATA_CLK
I/O
Tri-stated
Master mode off: Input for PCM Bit Clock OR DSD Bit Clock OR
SPDIF Input 1
Master mode on: Output for PCM Bit Clock
28
RESETB
I
Tri-stated
Master Reset / Power Down (active low)
Exposed
Pad
DGND
Ground
Ground
The exposed pad must be connected to Digital Ground
Note:
-
There are 7 N.C. (No Connect) pins. If desired, these pins can be connected to ground on the PCB to strengthen the
otherwise isolated pin pads.
-
The exposed pad should be connected to digital ground.
77
Содержание HD-AMP1/U1B/K1B/FN
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