46
Auto
The BIOS sets the value automatically.
AGP Driving
Control
Manual
The AGP Driving Value item below can be used to set the
value.
AGP Driving
Value
00-FF
This value sets the timing of the signal that the video card
driver uses to communicate over the AGP bus. The range is
from 00-FF Hex (00-255 DEC).
Disabled
AGP Fast
Write
Enabled
AGP Bus Timing Setting
Values
Meaning
Enabled
AGP Writes are executed with 1 wait state, enable only if your
AGP card support this.
AGP Master
1 WS Write
Disabled
AGP Write take longer than 1 wait state, default setting.
Enabled
AGP Reads are executed with 1 wait state, enable only if your
AGP card supports this.
AGP Master
1 WS Read
Disabled
AGP Reads take longer than 1 wait state, default setting.
CMOS SETUP UTILITY Copyright © 1984 – 2001 Award Software
CPU & PCI Bus Control
CPU to PCI Write Buffer
Enabled
Item Help
PCI Master 0 WS Write
Enabled
Menu Level
"
PCI Delay Transaction
Disabled
↑
↓
→
←
: Move Enter: Select + / - /PU / PD: value F10: save ESC: Exit F1: General Help
F5 : Previous Values F6:Fail-Safe Defaults F7: Optimized Defaults
PCI Bus Timing Setting
Values
Meaning
Enabled
When enabled CPU writes to PCI are buffered, the CPU will
not have to wait for the transaction to finish.
CPU to PCI
write Buffer
Disabled
The CPU will have to wait for each PCI write to finish befor a
new write can be initiated.
Enabled
PCI Master Wait stat set to 0 sec.
PCI Master 0
WS write
Disabled
PCI Master Wait stat do not set to 0 sec.
PCI delay
Transaction
Enabled
The chipset has a write buffer that supports delayed
transactions. Enable this item for PCI 2.1 compliance.