Lucky Star K7VA133, Руководство пользователя

Страница: 38 / 68

VT8371 System Board 36
3-1-3 Advanced Chipset Features
Bank 0/1(2/3, 4/5) DRAM Timing
This will determine the timing of SDRAM. The user can separately adjust the
timing of bank 0/1, 2/3, 4/5.
: SDRAM 10ns (default) — 10 nano second
: SDRAM 8ns, normal, medium, fast, turbo
SDRAM Cycle Length: control the DRAM page missing and row miss leadoff
timing.
:2
:3
(default)