Lucky Star 6VPM1, Руководство пользователя

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6VPM1 Main Board 35
Bank 0/1(2/3) DRAM Timing
This will determine the timing of SDRAM. The user can separately adjust the
timing of bank 0/1, 2/3.
:SDRAM 10ns (default)
:SDRAM 10ns, SDRAM 8ns, Normal, Medium, Fast, Turbo
SDRAM Cycle Length:
It controls the DRAM page missing and row miss
leadoff timing.
: 3( default)
: 2
DRAM Clock: If your DIMM modules are PC-100 compliant, select this
setting.
:Host CLK( default)
:HCLK-33
:HCLK+33
Memory Hole: this field enables a memory hole in main memory space. CPU
cycles matching an enabled hold are passed on to PCI note that a selection can
not be changed while the L2 cache is enabled.
:Disabled (default)
:1.5M - 16M
P2C/C2P Concurrency:
The CPU Host is free for other transactions while a PCI
transaction takes place.
:Disabled
:Enabled
(default)
Fast R-W Turn Around:
If a memory read is addressed to a location whose
latest write is being held in a buffer before being written to memory, the read is
satisfied through the buffer contents, and the read is not sent to the DRAM
.
:Disabled (default)
:Enabled
System BIOS cacheable