Lucky Star 5MVP4, Руководство пользователя

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VT8501 Main Board 44
Bank 0/1(2/3,4/5) DRAM Timing
This will determine the timing of SDRAM. The user can separately adjust the
timing of bank 0/1, 2/3, 4/5.
:SDRAM 10ns(default)
:SDRAM 10ns, SDRAM 8ns, Normal, Medium, Fast, Turbo
SDRAM Cycle Length: control the DRAM page missing and row miss leadoff
timing.
:2
:3(default)
Video BIOS cacheable: to define whether video BIOS area cacheable or not.
:Enabled (default)
:Disabled
System BIOS cacheable
define whether system BIOS area cacheable or not.
:Enabled (default)
:Disabled
Memory Hole:this field enable a memory hole in main memory space. CPU cycles
matching an enabled hold are passed on to PCI note that a selected can not be
changed while the L2 cache is enabled.
:Disabled (default)
:Enabled
Init Display First
To decide which function (AGP or PCI) to detect first.
:AGP(default)
The system will detect the onboard ”AGP” function first
:PCI slot
The system will detect PCI-interface VGA card.
Frame Buffer Size
:8M(default)