Lucent Technologies DDM-2000 OC-3, Руководство пользователя и обслуживания

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Circuit Pack Descriptions
Issue 3 June 2001 7-19
Timing Circuitry 7
DS1 External Timing. 7
Each TG circuit pack receives one DS1 reference signal
which it monitors and from which it recovers a clock signal. The recovered clock is
cross-fed to its companion TG circuit pack in the same shelf. If the microprocessor
on one TG circuit pack detects an incoming DS1 reference failure, it will signal the
microprocessor on the companion TG circuit pack. Thus, each TG circuit pack has
two DS1 references to choose from, one which is input directly and the other
cross-fed. Both TG circuit packs will normally select the same DS1 input. A loss of
both DS1 references will result in the TG circuit pack entering holdover mode.
Line Timing. 7
The reference signal feeding the phase-locked loop is selected from
the internal oscillator or a loop-timing clock derived from the incoming optical line.
In line (formerly loop)-timing mode, the OC-N line being selected for transmission
is also selected as the timing reference. The OC-3 line in function unit C selected
for transmission can optionally be selected for the timing reference. This selection
is under the control of the on-board microcontroller and the SYSCTL and is
dependent on the timing mode selected by the user via on-board selection
switches and the status of the references. Loss of both line (formerly loop)-timing
references will cause the TG circuit pack to go into holdover mode to maintain
system timing.
Free-Running. 7
For free-running operation, the TG derives timing from a
temperature-compensated, voltage-controlled crystal oscillator (TCVCXO) and a
digital phase-locked loop (DPLL) with a full temperature range end-of-life
accuracy of
±
15 parts-per-million (ppm) for the BBF2B TGS, and
±
4.6 ppm for the
BBF4 TG3.
DS1 Output. 7
The DS1 output port of the TG circuit pack can be provisioned for
either MULT or SYNC OUT mode via a hardware switch. In the SYNC OUT mode,
the derived DS1 output signal is generated from the incoming OC-N lines through
timing synchronization signals from the DDM-2000 OC-3 main OLIUs (main-1 or
main-2), which is the default, or function unit C by software command. In the
MULT mode, the DS1 output signal is buffered from an external DS1 input
reference. This external reference is typically a DS1 from a building integrated
timing supply (BITS).
Selection of these timing synchronization signals for the DS1 output in SYNC
mode is controlled by the SYSCTL circuit pack. This selection can be provisioned
via software command to "track" the active received side of the OC-N line used for
transmission, to always select its timing from the specified OC-3 line (main-1 or
main-2), or function unit C (fn-c-1 or fn-c-2), regardless of its maintenance
condition. Loss of timing reference for the DS1 output will result in the insertion of
DS1 AIS on this output port.
Holdover. 7
The TG circuit pack has an internal TCVCXO that will maintain shelf
timing in the event of an unprotected timing DS1 reference failure (that is,
holdover mode). The TGS (BBF2B) will maintain frequency stability to better than
a SONET minimum clock (SMC) accuracy. The TG3 (BBF4) will maintain