LSI Logic Confidential
10-6
Host Async Master Interface
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 10.2 Self-Paced Async Master Cycles with M_WAIT
BH CSO
DSO
BDT
BH
DT
CSO
DSO
DT
BH CSO
DSO
DT
BH CSO
DSO
BDT
BH
DT
CSO
DSO
DT
BH CSO
DSO
M_A
M_RD/WR
M_CS
M_UDS/LDS
M_D
68K Mode Read
68K Mode Write
68K Mode Burst Read
M_WAIT
M_A
M_CS
M_UWE/LWE
M_D
M_WAIT
M_OE
SRAM Mode Read
SRAM Mode Write
SRAM Mode Burst Read
DT
Содержание DMN-8600
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