Logitek ULTRA-VU, Руководство по эксплуатации и обслуживанию

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The first thing the DSP (IC11) does after reset is
copy its program from EPROM IC10 to internal RAM
memory. The program executes continuously. Note
that the 8 bit data bus is connected to the middle byte
of the DSP’s 24 bit data port.
Address decoder IC9 is used to reset the watch-
dog timer (IC8) and to connect the rear panel pro-
gramming switches (S1-S8) to the data bus via
resistor pack R20.
Front panel pushbutton switches S11 and S12 are
connected to the DSP data port via resistor pack
R19.
Serial data is sent synchronously (data, clock,
load) to the display driver chips via display connector
P6 in 32 bit strings. Data is placed on the top bit of the
DSP data port and clocked into the display drivers via
a write to address decoder IC9. Other writes to IC9
will load the 32 bit data string into the display drivers
via P6. A write to the left bargraph will also be de-
coded by IC8 and used to rest the watchdog timer.
The audio from the left input XLR connector J1 is
connected to a RF lowpass filter formed by R10, R11,
C1 and C2. The resistors also form a -9 dB pad with
the input impedance of the balanced receiver IC3.
IC3 provides an additional -6 dB pad between its in-
put and output. These pads allow +20 dBu input sig-
nals to be handled by the +/- 5 volt supply rails. The
output of IC3 is unity gain inverted by op-amp IC2a
and fed back to the reference input of IC3. This en-
ables IC3 to present an identical resistive load on its
two input pins. Input gain is adjusted via trimpot R1
which is the feedback resistor around gain stage
IC1a.
* * * * * * * * * IMPORTANT * * * * * * * * * *
Only replace IC2 with an op-amp which is slower
than the SSM2143 such as the TL072 used here. A
faster op-amp like the NE5532 will cause the output
of IC3 to oscillate.
* * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Signal from IC1a is fed through antialias filter R15
C4 and DC isolated by C3 before connecting to the
left input of the sigma delta analog to digital converter
IC7. The right channel connects to the converter via
similar circuitry.
The 12.288 MHz master clock input to the ADC is
generated by a crystal oscillator located on the DSP
chip. Combined left and right audio data is sent syn-
chronously (data, clock, frame sync) to the DSP in
64-bit strings. The DSP reset signal from IC8 is also
connected to the ADC. The DSP activates the reset
once a day which causes the ADC to perform a self
calibration routine for about half a second. If the me-
ter has undergone a substantial temperature
change, such as when it is first powered up, it may
generate noise up to -70 dBFS until it undergoes a
calibration cycle
4-7 Digital/Dual Input Control Card LG-265
Power from input connector P4 is connected to
voltage regulators IC2 and IC3 as well as display
board connector P6. IC2 is a +5VDC regulator that
feeds power to the analog front end of data receiver
IC1. The voltage is filtered by C2, C6 and clamped
against over voltage and voltage reversal by D1. IC3
is a +5VDC regulator that feeds the digital portion of
IC1 and all other circuits on the control board. The
output voltage is filtered by C3 and clamped by D2.
Distributed power filtering is supplied by C4,7,8,9 &
10.
On power up, the DSP is kept in reset by IC4 until
the power has stabilized, ensuring a good power on
reset. IC4 also contains a watchdog timer that will re-
set the DSP if its ST pin in not taken low at least once
every 150 mSec. This pin is normally pulsed low
every 5 mSec by the left bargraph load signal.
The DSP (IC6) is clocked by a 12.288 MHz crystal
oscillator consisting of Y1,C11,C12 and an internal
driver. IC6, pin43 is a buffered output of the oscillator.
The first thing the DSP (IC6) does after reset is
copy its startup program from EPROM IC5 to internal
RAM memory. That program executes once and then
loads the main program from EEPROM which exe-
cutes continuously. Note that the 8 bit data bus is con-
nected to the middle byte of the DSP’s 24 bit data
port.
The rear panel programming DIP switches S1-S8
are also connected to the DSP’s middle data byte via
isolation resistors R10 and control that portion of the
data bus when neither the DSP nor the EEPROM out-
put is active. The DSP inputs the switch positions via
a read to address zero.
Front panel pushbuttons S11,12,13 are connected
to the high byte of the DSP 24-bit data port via con-
nector P3 and isolation resistors R9.
Serial data is sent synchronously (data, clock,
load) to the display driver chips via the display con-
nector P6 in 32 bit strings. Data is placed on the top
bit (bit 23) of the DSP data port and clocked into the
display drivers via a write to address decoder IC7.
Other writes to IC7 will load the 32 bit data string into
the left bargraph, right bargraph or scale/indicator
driver groups via P6. A write to the left bargraph will
also reset the watchdog timer.
Two channel audio data is fed synchronously
(data, clock, frame sync) from digital data receiver
IC1 to DSP (IC6) serial port 1.
Encoded audio data enters the meter via XLR con-
nector J1 and is directly connected to the output con-
nector P2. Note that no buffering is applied to the loop
through output.
** Ultra-VU Operation & Service Manual ** Page 10