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SLIMbus Audio Bridge

User Manual

SLIMbus Audio Bridge User Manual V0,9 - Draft Version

Содержание SLIMbus

Страница 1: ...SLIMbus Audio Bridge User Manual SLIMbus Audio Bridge User Manual V0 9 Draft Version 1...

Страница 2: ...te 14 4 4 Incompatible Clock Gear 15 5 Bridge Connectivity 16 5 1 DC Supply Barrel Jack 16 5 2 Service Modular Jack 16 5 3 SPDIF IN OUT Jack 16 5 4 I2S Input HD15 Connector 17 5 5 I2S Output HD15 Conn...

Страница 3: ...ata ports must operate by pair and can be source or sink Additionally all sink ports must use the same Presence Rate Similarly all the source must use the same presence rate Note that the channel rate...

Страница 4: ...0x01C1 0x0001 0x01 0x00 0x01C100010100 Generic 0x01C1 0x0001 0x02 0x00 0x01C100010200 Component address 1 Device MID PID DI IV Enumeration Address Interface 0x01C1 0x0001 0x00 0x01 0x01C100010001 Fra...

Страница 5: ...I2S ASRC24 SB P01234567 OPR n a II IPR 48k Framer Off RF 1 The first line indicates the digital audio input source I2S or SPDIF the signal processing Asynchronous Sample Rate Converter or Direct follo...

Страница 6: ...k ports or all the source port the display will show ERROR instead of a presence rate value The following examples shows 4 configured ports Ports 1 and 2 are configured as source ports they output dat...

Страница 7: ...t the frequency displayed is only guarantied in PLL mode The bridge does not have a frequency meter When the source is either I2S or SMA the value indicates the required clock frequency It is the resp...

Страница 8: ...s a source and indicate to the framer what to write in the Framing Information bits 2 1 6 SLIMbus PHY The bridge features a Framer that can be active or inactive 5 SLIMbus PHY Bus Holder On SLIMbus Le...

Страница 9: ...lect MCLKI src Set I2S ASRC Set SPDIF ASRC Select DAC stream Select Framer Clk Set Framer BootRF Set Framer BootMod Set Comp Address Set SLIMbus Level Set Bus Hold Exit There are 11 parameters that ca...

Страница 10: ...6 SDO4 Ports 7 8 Select Framer Clk PLL 12MHz ref External Clk SMA Set Framer BootRF MHz RF 0 24 576 MHz RF 1 22 5792MHz RF 2 15 360 MHz RF 3 16 800 MHz RF 4 19 200 MHz RF 5 24 000 MHz RF 6 25 000 MHz...

Страница 11: ...hip which could lead to data loss The ASRC is the bridge between the 2 clock domains and is of such a high quality that the measured performances of the device under test will not be affected by the A...

Страница 12: ...LIMbus IP It is the responsibility of the user to ensure that the clock structure of the complete setup is suitable for an error free transmission of the audio samples 3 3 Concurrent use of PLL genera...

Страница 13: ...576 MHz 24 576 MHz 24 576 MHz RF 2 22 5792 MHz 22 578998 MHz Error of 202 Hz 22 5792 MHz RF 3 15 36 MHz 15 36 MHz 15 36 MHz RF 4 16 8 MHz 16 8 MHz 16 8 MHz RF 5 19 2 MHz 19 2 MHz 19 2 MHz RF 6 24 MHz...

Страница 14: ...the same I2S clocks MCLKO reference Therefore they must also use the same Presence Rate When 2 or more sink ports are not getting assigned the same Presence Rate the bridge will report an error and wi...

Страница 15: ...lies to both PLL and external clock operation 4 4 Incompatible Clock Gear The Clock Gear incompatibility only happens when the PLL operation is selected When the Clock Gear is too low to allow proper...

Страница 16: ...ive access to the bridge controller for eventual firmware upgrades Signal Name Pin Number Function MCLR 1 Input 3V3 2 Power GND 3 Ground PGD Serial Data 4 Bidir PGC Serial clock 5 Input Not Connected...

Страница 17: ...nal signal level is equal to 3 3V Maximum input level is 3 6V 5 5 I2S Output HD15 Connector The I2S Output interface is mapped on a HD15 male connector Signal Name Pin Number Function Master Clock MCL...

Страница 18: ...erface The MCLKO clock input is one of the three clock source for the I2S output interface The MCLKO clock output is a buffered output of the clock actually used by the IS output interface The Framer...

Страница 19: ...erate the audio clocks some care must be taken to ensure optimal data transmission and or reception The PLLs are configured once the associated Presence Rate is known The SLIMbus IP communicates that...

Страница 20: ...bits 5 slots and 24 bits 6 slots If the DL field is smaller than 4 slots the ASRC output word length will be set by default to 16 bits If the DL field is greater than 6 slots or set to Not Indicated...

Страница 21: ...nformation at boot time BOOT_RF 3 0 must use the coding or the RF field as described in the SLIMbus specification 0b0000 Not Indicated 0b0001 24 576MHz 0b0010 22 5792MHz 0b0011 15 36MHz 0b0100 16 8MHz...

Страница 22: ...ations are mutually exclusive The Port direction assignment through the CONNECT_SINK and CONNECT_SOURCE messages will define which of the I2S streams are used The 8 Ports bridge has additional capabil...

Страница 23: ...288 MHz HD15 I2S Output Interface Parameter Min Typical Max Unit I2S OUT signaling voltage output 3 3 V I2S OUT signaling voltage input 2 5 3 3 3 6 V Input pin capacitive load 15 pF Master clock freq...

Страница 24: ...ypical Max Unit Signaling voltage source impedance 0 Ohms 2 5 3 3 3 6 V Signaling voltage source impedance 50 Ohms 4 5 5 5 5 V Input impedance 100 Ohms Frequency 25 MHz MCLKO Output SMA Parameter Min...

Страница 25: ...PDIF and I2S Parameter Min Typical Max Unit THD N 0dBFs 24 bits resolution 140 dB Dynamic Range 142 dB Input Output Sampling Ratio 1 16 16 1 SLIMbus Electrical Performances Parameter Min Typical Max U...

Страница 26: ...6 6 6 6 6 6 6 6 6 6 6 6 32 6 6 6 6 6 6 6 6 6 6 6 6 6 16 6 6 6 6 6 6 6 6 6 6 6 6 6 8 6 6 6 6 6 6 6 6 6 6 6 6 6 4 6 6 6 6 6 6 6 6 6 6 6 6 6 Root Frequency 2 22 5792 MHz Sample Rate 192 96 48 24 12 176 8...

Страница 27: ...7 7 7 7 12 7 7 7 7 7 7 7 7 7 7 7 7 7 176 4 7 7 7 88 2 7 7 7 7 7 7 7 7 7 7 7 7 7 44 1 7 7 7 7 7 7 7 7 7 7 7 7 7 22 05 7 7 7 7 7 7 7 7 7 7 7 7 7 11 025 7 7 7 7 7 7 7 7 7 7 7 7 7 128 7 7 7 64 7 7 7 7 7 7...

Страница 28: ...Annex B Presence Rate Accuracy These tables only apply when input or output clocks are derived from the PLLs SLIMbus Audio Bridge User Manual V0 9 Draft Version 28...