TME-104P-CSR-LX800-R1V5.doc
Rev 1.5
42 (44)
5.2
I/O Address Map
The system chip set implements a number of registers in I/O address space. These registers occupy
the following map in the I/O space.
Address Range
Description
0000 - 000F
DMA-Controller
0020 - 0021
Programmable Interrupt controller
002E - 002F
System
0040 - 0043
System timer
0048 - 004B
System timer
004E - 004F
Super I/O
0060 - 0060
Keyboard
0061 - 0061
System speaker
0064 - 0064
Keyboard
0070 - 0073
System CMOS/Real-time clock
0080 - 008F
DMA-Controller
0092 - 0092
System
00A0 - 00A1
Programmable Interrupt controller
00C0 - 00DF
DDMA-Controller
00F0 - 00FF
Numeric Coprocessor
0100 - 017F
PCI-
ISA Bridge Positive Decode Range 1
0180 - 01BF
PCI-
ISA Bridge Positive Decode Range 2
01C0 - 01CF
PCI-
ISA Bridge Positive Decode Range 3
01F0 – 01FF
IDE Controller
0200 - 027F
PCI-
ISA Bridge Positive Decode Range 4
0279 - 0279
ISA PnP-Data port
0295 - 0296
LPC-Bus
02F8 - 02FF
COM2
0300 - 033F
PCI-
ISA Bridge Positive Decode Range 5
0340 - 035F
PCI-
ISA Bridge Positive Decode Range 6
0378 - 037F
LPT1
03B0 - 03BA
Advanced Micro Devices Win XP Graphics Driver
03C0 - 03DF
Advanced Micro Devices Win XP Graphics Driver
03F0 - 03F7
Standard-Floppy controller
03F8 - 03FF
COM1
0480 - 048F
DMA-Controller
04D0 - 04D1
Programmable Interrupt controller
0A79 - 0A79
ISAPnP-Data port
1200 - 1207
SPI-Flash
1220 - 1227
Simple-I/O (default)
DF80 - DFFF
Not used
EFF0 - EFFF
Standard-Dual-Channel-PCI-IDE-Controller