Page 11
CHANNEL SELECTION
Parallel Selection
All HP-3 transmitter models feature
eight parallel selectable channels.
Parallel mode is selected by
grounding the mode pin. In this mode,
channel selection is determined by
the logic states of pins CS0-CS2 as
shown in Figure 20. In this table a "0"
represents ground and a "1" the positive supply. The on-board microprocessor
performs all PLL loading functions, eliminating external programming and
allowing channel selection via DIP switches or a product's processor.
Serial Selection
In addition to the parallel mode, PS versions of the HP-3 also feature 100 serially
selectable channels. The serial mode is entered when the mode pin is left open
or held high. In this condition CS1 and CS2 become a synchronous serial port
with CS1 serving as the clock line and CS2 as the data line. The module is easily
programmed by sending and latching the binary number (0-100) of the desired
channel (
see page 22 for channel selection table
). With no additional effort the
module's on-board microprocessor handles the complex PLL loading functions.
The serial mode is
straightforward, however,
minimum timings and bit
order must be followed.
Loading is initiated by
taking the clock line high
and the data line low as
shown. The eight-bit
channel number is then
clocked in one bit at a time
with the LSB first.
Figure 20: Parallel Channel Select Table
Variable Data
Note 3
Note 2
Note 1
1
2
3
4
5
6
7
8
T1
25
µ
s
T2
5
µ
s
T3
8
µ
s
T4
5
µ
s
Data
Clock
T0
1ms
(T0)
Minimum time between packets or prior to data startup...................................1mS min.
(T1)
Data-LO/Clock-HI to Data-LO/Clock-LO..............................................................25µS min.
(T2)
Clock-LO to Clock-HI..............................................................................................5µS min.
(T3)
Clock-HI to Clock-LO..............................................................................................8µS min.
(T4)
Data-HI/Clock-HI......................................................................................................5µS min.
Total Packet Time ..........................................................................................................157µS min.
1) Loading begins when clock line is high and data line is taken low.
2) Ensure that the edge is fully risen prior to the high-clock transition.
3) Both lines high - triggers automatic latch
Figure 21: PLL Serial Programming Timing Table
There is no maximum time for this process, only the minimum times which must be
observed. After the eighth bit both the clock and data lines should be taken high to
trigger the automatic data latch. A typical software routine can complete the loading
sequence in under 200µS. A sample routine is available on the Linx website.
NOTE: When the module is powered up in the serial mode it will default to channel 50 until
programmed by user software. This allows testing apart from external programming and
prevents out-of-band operation. When programmed properly, the dwell time on this default
channel can be less than 200µS. Channel 50 is not counted as a usable channel since
transmitters defaulting to the channel might interfere with a transmitter intentionally
occupying the channel. If a loading error occurs, such as a channel number >100 or a
timing problem, the receiver will default to serial channel 0. This is useful for debugging as
it verifies serial port activity.
CS2
CS1
CS0
Channel Frequency
0
0
0
0
903.37
0
0
1
1
906.37
0
1
0
2
907.87
0
1
1
3
909.37
1
0
0
4
912.37
1
0
1
5
915.37
1
1
0
6
919.87
1
1
1
7
921.37
