Linx EVM-900-PRO, Руководство по данным

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Transmitting Packets
In default operation when transmitting, the host microcontroller writes bytes
to the CMD_DATA_IN line while the CMD line is held high at the baud rate
selected by the
UARTBAUD register. The incoming bytes are buffered until
one of the following conditions triggers the packet to be transmitted:
1. The number of bytes in the buffer exceeds the value in the Byte Count
Trigger ( BCTRIG ) register.
2. The time since the last received byte exceeds the value in the Data
Timeout ( DATATO ) register.
3. A SENDP command is written to the CMD register.
4. The CMD line is taken low with option PKOPT: TXnCMD = 1.
5. The number of buffered bytes exceeds what can be sent before the
radio must hop channels.
The first four conditions can be controlled by the host microcontroller. In
the last case, the module transmits what it can in the remaining time then
sends the rest on the next channel. This can cause the data to be divided
up into multiple packets and is not within the control of the host micro.
In cases where all data needs to be sent in the same packet or where the
microcontroller needs greater control over the radio, the HumPRO
TM
offers
explicit control of packet transmission with options in the PKTOPT register.
When the TXPKT option is enabled ( PKTOPT register, bit 0 = 1), the data is
held until a SENDP command is written to the CMD register. Alternatively,
if option TXnCMD is enabled (
PKTOPT register, bit 1 = 1), then lowering
the CMD line triggers the packet transmission, reducing the number of
UART transactions that are required. The
BCTRIG , DATATO and hop-timing
conditions are ignored when the TXPKT option is enabled.
Once triggered, the transmitted packet contains the bytes in the buffer as
of the trigger event, even if more data bytes are received before the packet
can be sent. Multiple outgoing packets can be buffered in this way.
If the full packet cannot be sent in the time remaining on the current
channel, then it is held until the module hops to the next channel.
This option gives the host microcontroller very fine control over when
packets are transmitted and what they contain.
Receiving Packets
In default operation when receiving valid packets, the module outputs all
received bytes as soon as the packet is validated (CRC checks pass if
unencrypted or key-based verification if encrypted) and if the addressing
permits it at the baud rate selected by the
UARTBAUD register. No
command or control bytes are output and no action is required of an
external microcontroller. The first byte from a packet directly follows the last
byte of the previously received packet.
In cases where the host microcontroller needs more control over the data
or where dynamic configuration changes could set up race conditions
between incoming data and outgoing commands, the module offers
explicit control over received packets.
When the RXPKT option is enabled ( PKTOPT register, bit 2 = 1), received
data is output on the CMD_DATA_OUT line one packet at a time after a
GETPH, GETPD, or GETPHD command is written to the
CMD register.
Writing one of these commands begins the received packet transfer cycle.
Two lines are used as flow control and indicators during the transfer cycle.
The CMD line is controlled by the host microcontroller. The module uses
either the CTS line or the CRESP line as a status line, depending on the
state of the RXP_CTS option in the
PKOPT register.
When a valid packet is received, the EX_RXWAIT exception flag is set in
the
EEXFLAG 1 register. If the corresponding bit in the EEXMASK 1 register
is set, then the EX line goes high. The host microcontroller can monitor
the EX line or periodically check the
EEXFLAG or LSTATUS registers to
determine if data is ready to be read.
The transfer cycle is begun by writing a Get Packet Header (GETPH),
Get Packet Data (GETPD), or Get Packet Header and Data (GETPHD)
command to the
CMD register. The module sends the command ACK byte
and sets the selected status line high. Once the status line goes high, the
host microcontroller sets the CMD line high and the module outputs the
received data. The command sent determines whether the bytes sent are
the header, data, or header followed by data.
When all packet bytes have been sent the control line goes low. When
the host microcontroller detects that the line is low, it sets CMD low,
completing the transfer cycle. The cycle is shown in Figure 21.