23
LTC3736
3736fa
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10
µ
F capacitor would require a 250
µ
s rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736. These items are illustrated in the layout diagram
of Figure 13. Figure 14 depicts the current waveforms
present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
at the FETs. It is better to have two separate, smaller valued
input capacitors (e.g., two 10
µ
F—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22
µ
F) that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, I
TH
compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Each channel should have its own power ground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
The PGND pins on the LTC3736 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the V
FB
pins. The
trace connecting the top feedback resistor (R
B
) to the
output capacitor should be a Kelvin trace. The I
TH
compen-
sation components should also be very close to the
LTC3736.
4) The current sense traces (SENSE
+
and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, I
TH
compensation components and the current
sense pins (SENSE
+
and SW).
APPLICATIO S I FOR ATIO
W
U
U
U
SW1
IPRG1
V
FB1
I
TH1
IPRG2
PLLLPF
SGND
V
IN
TRACK
V
FB2
I
TH2
PGOOD
SENSE1
+
PGND
BG1
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
+
SW2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LTC3736EGN
+
+
C
OUT1
C
OUT2
C
VIN1
C
VIN
V
OUT1
V
OUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
3736 F13
L1
L2
MN1
MP1
MN2
MP2
V
IN
C
VIN2
Figure 13. LTC3736 Layout Diagram
