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LTC2172-12/ 

LTC2171-12/LTC2170-12

19

21721012fb

FuncTional block DiagraM

PLL

DATA

SERIALIZER

SAMPLE-

AND-HOLD

12-BIT

ADC CORE

CHANNEL 1

ANALOG

INPUT

12-BIT

ADC CORE

CHANNEL 2

ANALOG

INPUT

12-BIT

ADC CORE

CHANNEL 3

ANALOG

INPUT

12-BIT

ADC CORE

CHANNEL 4

ANALOG

INPUT

1.8V

V

DD

1.8V

ENC

+

ENC

–

OV

DD

V

DD

/2

DIFF

REF

AMP

REF

BUF

2.2µF

0.1µF

0.1µF

0.1µF

REFH

REFL

RANGE

SELECT

1.25V

REFERENCE

REFH

REFL

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

DATA

CLOCK OUT
FRAME

OGND

VCM12

GND

VCM34

0.1µF

0.1µF

SDO

CS

SENSE

V

REF

1µF

MODE

CONTROL

REGISTERS

SCK

PAR/

SER

SDI

217212 F01

SAMPLE-

AND-HOLD

SAMPLE-

AND-HOLD

SAMPLE-

AND-HOLD

Figure 1. Functional Block Diagram

Содержание LTC2170-12

Страница 1: ...at full speed for a wide range of clock duty cycles LTC2172 12 65Msps 2 Tone FFT fIN 70MHz and 75MHz Features Applications n 4 Channel Simultaneous Sampling ADC n 71dB SNR n 90dB SFDR n Low Power 306...

Страница 2: ...OUT4A 32 31 30 29 28 27 9 10 11 12 13 14 TJMAX 150 C JA 28 C W EXPOSED PAD PIN 53 IS GND MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPE...

Страница 3: ...Offset Matching 3 3 3 mV Transition Noise External Reference 0 32 0 32 0 32 LSBRMS Analog Input The l denotes the specifications which apply over the full operating temperature range otherwise specifi...

Страница 4: ...0MHz Input 140MHz Input l 85 90 90 90 90 85 90 90 90 90 85 90 90 90 90 dBFS dBFS dBFS dBFS S N D Signal to Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input l 69 1 70 9 70 9...

Страница 5: ...ing Mode VIH High Level Input Voltage VDD 1 8V l 1 3 V VIL Low Level Input Voltage VDD 1 8V l 0 6 V IIN Input Current VIN 0V to 3 6V l 10 10 A CIN Input Capacitance 3 pF SDO OUTPUT Serial Programming...

Страница 6: ...h apply over the full operating temperature range otherwise specifications are at TA 25 C Note 9 SYMBOL PARAMETER CONDITIONS LTC2172 12 LTC2171 12 LTC2170 12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX...

Страница 7: ...elow GND or above VDD without latchup Note 4 When these pin voltages are taken below GND they will be clamped by internal diodes When these pin voltages are taken above VDD they will not be clamped by...

Страница 8: ...ING NORMAL NON OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0 SEE THE DATA FORMAT SECTION FOR MORE DETAILS 217212 TD02 tAP N 2 N 1 N ANALOG INPUT ENC DCO FR ENC DCO FR OUT A NOTE THAT IN THIS MODE...

Страница 9: ...D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D11 D10 D9 D8 tENCH tENCL tSER DX AND DY ARE EXTRA NON DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14 BIT VERSIONS OF THESE A Ds DURING NORMAL NON OVERRANGED...

Страница 10: ...TS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14 BIT VERSIONS OF THESE A Ds DURING NORMAL NON OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0 SEE THE DATA FORMAT SECTION FOR MORE DETAILS timing DI...

Страница 11: ...ack Mode A6 tS tDS A5 A4 A3 A2 A1 A0 XX D7 D6 D5 D4 D3 D2 D1 D0 XX XX XX XX XX XX XX CS SCK SDI R W SDO HIGH IMPEDANCE tDH tDO tSCK tH A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 217212 TD07 CS SCK S...

Страница 12: ...3 0 10 20 30 OUTPUT CODE 0 1 0 0 4 0 6 0 8 INL ERROR LSB 0 2 0 0 2 0 8 0 4 0 6 1 0 1024 2048 3072 4096 217212 G01 OUTPUT CODE 0 1 0 0 4 0 2 0 6 0 8 DNL ERROR LSB 0 0 4 0 2 0 6 0 8 1 0 1024 2048 3072 4...

Страница 13: ...BFS 90 100 110 70 60 50 40 30 20 10 0 217212 G12 dBFS dBc SENSE PIN V 0 6 71 68 69 70 67 66 72 SNR dBFS 0 7 0 8 0 9 1 1 1 2 1 3 1 217212 G15 OUTPUT CODE 0 1 0 0 4 0 6 0 8 INL ERROR LSB 0 2 0 0 2 0 4 0...

Страница 14: ...REQUENCY MHz 0 100 110 120 70 60 80 90 AMPLITUDE dBFS 50 30 40 20 10 0 10 20 217212 G26 FREQUENCY MHz 0 100 110 120 70 60 80 90 AMPLITUDE dBFS 50 30 40 20 10 0 10 20 217212 G27 OUTPUT CODE 2049 2000 0...

Страница 15: ...7212 G35 OUTPUT CODE 0 1 0 0 4 0 6 0 8 INL ERROR LSB 0 2 0 0 4 0 6 0 2 0 8 1 0 1024 2048 3072 4096 217212 G41 OUTPUT CODE 0 1 0 0 4 0 2 0 6 0 8 DNL ERROR LSB 0 0 4 0 2 0 6 0 8 1 0 1024 2048 3072 4096...

Страница 16: ...70MHz 2V Range 25Msps LTC2170 12 SFDR vs Input Frequency 1dBFS 2V Range 25Msps LTC2170 12 IVDD vs Sample Rate 5MHz Sine Wave Input 1dBFS LTC2170 12 SNR vs SENSE fIN 5MHz 1dBFS Typical Performance Char...

Страница 17: ...WhenCSislow SCK is enabled for shifting data on SDI into the mode controlregisters Inparallelprogrammingmode PAR SER VDD CS selects two lane or one lane output mode CS can be driven with 1 8V to 3 3V...

Страница 18: ...selects the internal reference and a 0 5V input range An external reference between 0 625V and 1 3V applied to SENSE selects an input range of 0 8 VSENSE LVDS Outputs The following pins are differenti...

Страница 19: ...T 12 BIT ADC CORE CHANNEL 4 ANALOG INPUT 1 8V VDD 1 8V ENC ENC OVDD VDD 2 DIFF REF AMP REF BUF 2 2 F 0 1 F 0 1 F 0 1 F REFH REFL RANGE SELECT 1 25V REFERENCE REFH REFL OUT1A OUT1B OUT2A OUT2B OUT3A OU...

Страница 20: ...or the 2V input range the inputs should swing from VCM 0 5V to VCM 0 5V There should be a 180 phase difference between the inputs The four channels are simultaneously sampled by a shared encode circui...

Страница 21: ...es 4 to 6 should convert the signal to differential before driving the A D Figure 5 Recommended Front End Circuit for Input Frequencies from 170MHz to 300MHz Figure 6 Recommended Front End Circuit for...

Страница 22: ...code Input The signal quality of the encode inputs strongly affects the A D noise performance The encode inputs should be treated as analog signals do not route them next to digital traces on the circ...

Страница 23: ...allows the duty cycle of the applied encode signal to vary from 30 to 70 Applications Information In the serial programming mode it is possible to disable the duty cycle stabilizer but this is not rec...

Страница 24: ...12 or 25MHz LTC2170 12 SERIALIZATION MODE MAXIMUM SAMPLING FREQUENCY fS MHz DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE 2 Lane 16 Bit Serialization 65 4 fS fS 8 fS 2 Lane 14 Bit Serialization 65 3 5...

Страница 25: ...al program ming mode or by SDI parallel programming mode The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF REFH and REFL For the suggested val...

Страница 26: ...rial programming is used the mode control registers shouldbeprogrammedassoonaspossibleafterthepower supplies turn on and are stable The first serial command must be a software reset which will reset a...

Страница 27: ...bled 1 Digital Outputs are disabled Bits 2 0 OUTMODE2 OUTMODE0 Digital Output Mode Control Bits 000 2 Lanes 16 Bit Serialization 001 2 Lanes 14 Bit Serialization 010 2 Lanes 12 Bit Serialization 011 N...

Страница 28: ...citor between REFH and REFL This capacitor should be on the same side of the circuit board as the A D and as close to the device as possible 1 5mm or less Size 0402 ceramic capacitors are recommended...

Страница 29: ...LTC2172 12 LTC2171 12 LTC2170 12 29 21721012fb Typical Applications Silkscreen Top Top Side Inner Layer 2 GND Inner Layer 3...

Страница 30: ...LTC2172 12 LTC2171 12 LTC2170 12 30 21721012fb TYPICAL Applications Inner Layer 4 Inner Layer 5 Power Bottom Side Silkscreen Bottom...

Страница 31: ...27 V DD V DD ENC ENC CS SCK SDI GND OUT4B OUT4B OUT4A OUT4A 16 15 VDD 17 18 19 20 21 22 23 24 25 26 V DD V DD SENSE GND V REF PAR SER SDO GND OUT1A OUT1A OUT1B OUT1B 51 52 50 49 48 SDO VDD PAR SER SE...

Страница 32: ...ATED 6 SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK SEE NOTE 6 PIN 1 NOTCH R 0 30 TYP OR 0 35 45 C CHAMFER 0 40 0 10 52 51 1 2 BOTTOM VIEW EXPOSED...

Страница 33: ...d herein will not infringe on existing patent rights Revision History REV DATE DESCRIPTION PAGE NUMBER A 03 10 Changed Sampling Frequency Max for LTC2171 12 from 45MHz to 40MHz in the Timing Character...

Страница 34: ...V Dual ADCs Ultralow Power 203mW 243mW 299mW 73 1dB SNR 88dB SFDR Serial LVDS Outputs 6mm 6mm QFN 40 LTC2266 12 LTC2267 12 LTC2268 12 12 Bit 80Msps 105Msps 125Msps 1 8V Dual ADCs Ultralow Power 200mW...

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