5
DEMO MANUAL DC290
NO-DESIGN SWITCHER
+
–
+
–
+
–
+
–
+
–
OVDET
EA
+
–
I
RCMP
+
–
I
COMP
8
7
3
1
RUN
PLL LPF
VCO
X
Y
Y = “0” ONLY WHEN X IS A CONSTANT “1”
BURST
DEFEAT
SLOPE
COMP
OSC
SYNC/MODE
0.6V
FREQ
SHIFT
0.8V
0.85V
0.8V REF
SHUTDOWN
0.45V
0.8V
SLEEP
V
IN
V
IN
V
IN
V
IN
I
TH
SLEEP
V
FB
EN
BURST
V
IN
2
S
R
RS LATCH
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI
SHOOT-
THRU
Q
Q
6
Ω
6
SW
5
GND
dc290A BD
4
OPERATIO
U
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 80kHz, one-seventh of the
nominal frequency. This frequency foldback ensures that
the inductor current has more time to decay, thereby
preventing runaway. The oscillator’s frequency will
progressively increase to 550kHz (or the synchronized
frequency) when V
FB
rises above 0.3V.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC1877
and the LTC1878 to allow the oscillator to be synchronized
to an external source connected to the SYNC/MODE pin.
The output of the phase detector at the PLL LPF pin
operates over a 0V to 2.4V range, corresponding to
400kHz to 700kHz. When locked, the PLL aligns the
turn-on of the MOSFETs to the rising edge of the synchro-
nizing signal.
When the LTC1877 or the LTC1878 is clocked by an
external source, Burst Mode operation is disabled; the
LTC1877 or the LTC1878 then operates in PWM pulse
skipping mode. In this mode, when the output load is very
low, the current comparator, I
COMP
, may remain tripped
for several cycles and force the main switch to stay off for
the same number of cycles. Increasing the output load
slightly allows constant frequency PWM operation to
resume.
Frequency synchronization is inhibited when the feedback
voltage, V
FB
, is below 0.6V. This prevents the external
clock from interfering with the frequency foldback for
short-circuit protection.
Figure 3. Functional Block Diagram
