LTC1760
40
1760fc
For more information
www.linear.com/LTC1760
Calculating IC Power Dissipation
The power dissipation of the LTC1760 is dependent
upon the gate charge of Q
TG
and Q
BG
.(Refer to Typical
Application). The gate charge is determined from the
manufacturer’s data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the FET.
P
D
= (V
DCIN
– V
VCC
) • f
OSC
• (Q
TG
+ Q
BG
) + V
DCIN
•
I
DCIN_CHG
– V
VCC
• (I
SAFETY1
+ I
SAFETY2
)
where:
I
DCIN_CHG
, I
SAFETY1
, I
SAFETY2
are defined in the
previous section.
Example:
V
VCC
= 5.2V, V
DCIN
= 19V, f
OSC
= 345kHz, Q
TG
=
Q
BG
= 15nC, I
DCIN_CHG
= 2.62mA, I
SAFETY1
=
I
SAFETY2
= 218µA.
P
D
= 190mW
V
SET
/I
SET
Capacitors
Capacitor C7 is used to filter the delta-sigma modulation
frequency components to a level which is essentially DC.
Acceptable voltage ripple at I
SET
is about 10mV
P-P
. Since
the period of the delta-sigma switch closure, T
∆
S
, is about
10µs and the internal I
DAC
resistor, R
SET
, is 18.77k, the
ripple voltage can be approximated by:
Δ
V
ISET
=
V
REF
• T
Δ
∑
R
SET
• C7
Then the equation to extract C7 is:
C7
=
V
REF
• T
Δ ∑
Δ
V
ISET
•R
SET
= 0.8/0.01/18.77k(10µs)
@
0.043µF
In order to prevent overshoot during start-up transients
the time constant associated with C7 must be shorter than
the time constant of C5 at the I
TH
pin. If C7 is increased
to improve ripple rejection, then C5 should be increased
proportionally and charger response time to average cur-
rent variation will degrade.
Capacitors C
B1
and C
B2
are used to filter the V
DAC
delta-
sigma modulation frequency components to a level which
is essentially DC. C
B2
is the primary filter capacitor and
CB1 is used to provide a zero in the response to cancel
the pole associated with C
B2
. Acceptable voltage ripple
at V
SET
is about 10mV
P-P
. Since the period of the delta-
sigma switch closure, T
∆
S
, is about 11µs and the internal
V
DAC
resistor, R
VSET
, is 7.2kΩ, the ripple voltage can be
approximated by:
Δ
V
VSET
=
V
REF
• T
Δ ∑
R
VSET
C
B1
||C
B2
(
)
Then the equation to extract C
B1
|| C
B2
is:
C
B1
||C
B2
=
V
REF
• T
Δ ∑
R
VSET
Δ
V
VSET
C
B2
should be 10
×
to 20
×
C
B1
to divide the ripple voltage
present at the charger output. Therefore C
B1
= 0.01µF and
C
B2
= 0.1µF are good starting values. In order to prevent
overshoot during start-up transients the time constant as-
sociated with C
B2
must be shorter than the time constant
of C5 at the I
TH
pin. If C
B2
is increased to improve ripple
rejection, then C5 should be increased proportionally and
charger response time to voltage variation will degrade.
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application
section), the input capacitor (C
IN
) is assumed to absorb all
input switching ripple current in the converter, so it must
have adequate ripple current rating. Worst-case RMS ripple
current will be equal to one half of output charging current.
Actual capacitance value is not critical. Solid tantalum
low ESR capacitors have high ripple current rating in a
relatively small surface mount package,
but caution must
be used when tantalum capacitors are used for input or
output bypass
. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capaci-
tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “Surge Robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.
APPLICATIONS INFORMATION
