LT3956
3956f
Loop Compensation
The LT3956 uses an internal transconductance error ampli-
fier whose V
C
output compensates the control loop. The
external inductor, output capacitor and the compensation
resistor and capacitor determine the loop stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor at V
C
are selected to optimize control loop
response and stability. For typical LED applications, a 4.7nF
compensation capacitor at V
C
is adequate, and a series re-
sistor should always be used to increase the slew rate on
the V
C
pin to maintain tighter regulation of LED current dur-
ing fast transients on the input supply to the converter.
Board Layout
The high speed operation of the LT3956 demands careful
attention to board layout and component placement. The
exposed pads of the package are important for thermal
management of the IC. It is crucial to achieve a good electri-
cal and thermal contact between the GND exposed pad and
the ground plane of the board. To reduce electromagnetic
interference (EMI), it is important to minimize the area of
the high dV/dt switching node between the inductor, SW
pin and anode of the Schottky rectifier. Use a ground plane
under the switching node to eliminate interplane coupling
to sensitive signals. The lengths of the high dI/dt traces:
1) from the switch node through the switch to PGND, and
2) from the switch node through the Schottky rectifier and
filter capacitor to PGND, should be minimized. The ground
points of these two switching current traces should come
to a common point then connect to the ground plane at the
PGND pin of the LT3956 through a separate via to Pin 12,
as shown in the suggested layout (Figure 5). Likewise, the
ground terminal of the bypass capacitor for the INTV
CC
regulator should be placed near the GND of the IC. The
ground for the compensation network and other DC control
signals should be star connected to the GND Exposed Pad
of the IC. Do not extensively route high impedance signals
such as FB and V
C
, as they may pick up switching noise.
Since there is a small variable DC input bias current to
the ISN and ISP inputs, resistance in series with these
pins should be minimized to avoid creating an offset in
the current sense threshold.
applicaTions inForMaTion
Figure 5. Boost Converter Suggested Layout
3
VIA FROM LED
+
LED
–
LED
+
3956 F05
LT3956
GND
SW
VMODE
PWM
CTRL
CV
CC
VIAS TO GND PLANE
VIAS TO SW PLANE
VIAS FROM
PGND
PGND
VIAS
R
T
C
SS
V
OUT
VIA
LED
+
VIA
VIA FROM V
OUT
R
C
C
C
V
IN
CV
IN
PGND
L1
R1 R2
R3
R4
M1
C
OUT
C
OUT
D1
1
2
12 13 14 15 16 17
36 35 34 33 32 31 30
21
23
24
25
27
28
8
6
4
3
2
1
20
9
10
V
IN
R
S