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dc2581af

DEMO MANUAL DC2581A

DC2581A SETUP

Layout

As with any high performance ADC, this part is sensitive 

to layout. The area immediately surrounding the ADC on 

the DC2581A should be used as a guideline for placement, 

and routing of the various components associated with 

the ADC. Here are some things to remember when laying 

out a board for the LTC2341. A ground plane is necessary 

to obtain maximum performance. Keep bypass capacitors 

as close to supply pins as possible. Use individual low 

impedance  returns  for  all  bypass  capacitors.  Use  of  a 

symmetrical layout around the analog inputs will minimize 

the effects of parasitic elements. Shield analog input traces 

with ground to minimize coupling from other traces. Keep 

traces as short as possible. 

Component Selection

When driving a low noise, low distortion ADC such as the 

LTC2341, component selection is important so as to not 

degrade performance. Resistors should have low values 

to minimize noise and distortion. Metal film resistors are 

recommended to reduce distortion caused by self heat-

ing. Because of their low voltage coefficients, to further 

reduce distortion NPO or silver mica capacitors should be 

used. Any buffer used to drive the LTC2341 should have 

low distortion, low noise and a fast settling time such as 

the LT6237.

Содержание DC2581A

Страница 1: ...he DC590 DC2026 and DC890 data collection boards Use the DC590 DC2026 to L LT LTC LTM Linear Technology and the Linear logo are registered trademarks and PScope QuikEval and SoftSpan are trademarks of Linear Technology Corporation All other trademarks are the property of their respective owners demonstrate DC performance such as peak to peak noise and DC linearity Use the DC890 if precise sampling...

Страница 2: ... The PScope software should recognize the DC2581A and configure itself automatically Click the Collect button See Figure 3 to begin acquiring data The Collect button then changes to Pause which can be clicked to stop data acquisition DC590 DC2026 QUICK START PROCEDURE IMPORTANT To avoid damage to the DC2581A make sure that VCCIO JP6 of the DC590 JP3 of the DC2026 of the DC590 DC2026 is set to 3 3V...

Страница 3: ...refore it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate The ratio of clock frequency to conversion rate is shown in the Assembly Options table If theclockinputistobedrivenwithlogic itisrecommended that the 49 9Ω termination resistor R4 be removed Driving R4 with discrete logic may result in slow rising edges Theseslowrisingedgesmaycompromi...

Страница 4: ...n the Set Demo Bd Options button in the PScope tool bar shown in Figure 4 This will open the Configure Channels menu of Figure 5 In this menu it is possible to set the input signal range setting for each channel There is also a button to return PScope to the default DC2581A settings which are optimized for the default hardware settings of the DC2581A Thereareanumberofscenariosthatcanproducemislead...

Страница 5: ...of a symmetricallayoutaroundtheanaloginputswillminimize theeffectsofparasiticelements Shieldanaloginputtraces with ground to minimize coupling from other traces Keep traces as short as possible Component Selection When driving a low noise low distortion ADC such as the LTC2341 component selection is important so as to not degrade performance Resistors should have low values to minimize noise and d...

Страница 6: ...6 dc2581af DEMO MANUAL DC2581A DC2581A SETUP Figure 3 PScope Screen Shot Figure 4 PScope Tool Bar ...

Страница 7: ...7 dc2581af DEMO MANUAL DC2581A DC2581A SETUP Figure 5 PScope Configuration Menu ...

Страница 8: ...8 dc2581af DEMO MANUAL DC2581A DC2581A SETUP Figure 6 QuikEval Screen Shot Figure 7 QuikEval Configuration Menu ...

Страница 9: ...s CMOS Only CMOS is currently supported Definitions P1 DC890 interface is used to communicate with the DC890 controller J1 CLK provides the master clock for the DC2581A when interfaced to the DC890 J2 FPGA PROGRAM is used to program the FPGA This is for factory use only JP4 EEPROM is for factory use only The default posi tion is WP JP5 JP8 AIN0 AIN1 can be used to short individual AIN inputs to gr...

Страница 10: ...UDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES The user assumes all responsibility and liability for proper and safe handling of the goods Further the user releases LTC from all claims arising from the handling or use of the goo...

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