3
dc2581af
DEMO MANUAL DC2581A
DC2581A SETUP
+
–
+
–
AIN0
AIN0
+
AIN0
–
V
CM
R107
49.9Ω
U25B
LT6237IDD
U25A
LT6237IDD
C96
0.1µF
C94
1000pF
C98
OPT
C116
OPT
R129
1k
R108
24.9Ω
R123
24.9Ω
C104
0.1µF
V
CC
V
EE
R124
49.9Ω
C100
39pF
C112
39pF
EN
C102
1000pF
DC2581a F02
R113
0Ω
R119
1k
DC Power
The DC2581A requires ±9VDC and draws +132mA/–52mA.
Most of the supply current is consumed by the FPGA, op
amps, regulators and discrete logic on the board. The
±9VDC input voltage powers the ADC through LT1763
regulators which provide protection against accidental
reverse bias. Additional regulators provide power for the
FPGA and op amps.
Clock Source
You must provide a low jitter 2.5V
P-P
sine or square wave
to the clock input, J1. The clock input is AC coupled so the
DC level of the clock signal is not important. A generator
such as the Rohde & Schwarz SMB100A high speed clock
source is recommended to drive the clock input. Even a
good generator can start to produce noticeable jitter at
low frequencies. Therefore it is recommended for lower
sample rates to divide down a higher frequency clock to
the desired sample rate. The ratio of clock frequency to
conversion rate is shown in the Assembly Options table. If
the clock input is to be driven with logic, it is recommended
that the 49.9Ω termination resistor (R4) be removed.
Driving R4 with discrete logic may result in slow rising
edges. These slow rising edges may compromise the SNR
of the converter in the presence of high-amplitude higher
frequency input signals.
Data Output
Parallel data output from this board (0V to 2.5V default),
if not connected to the DC890, can be acquired by a logic
analyzer, and subsequently imported into a spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can
be fed directly into an application circuit. Use pin 50 of
P1 to latch the data. The data should be latched using the
negative edge of this signal. The data output signal levels
at P1 can also be increased to 0V-3.3V if the application
circuit requires a higher voltage. This is accomplished by
moving JP2 to the 3.3V position.
Figure 2. 0V–4.096V Single-Ended to Fully Differential DC Coupled Driver