3
dc1974f
DEMO MANUAL DC1974
HARDWARE SETUP
SMAs
J1
: AINA – Analog input for channel A – Apply a signal to
J1 from a 50Ω driver. Filters are required for data sheet
performance.
J2:
AINB – Analog input for channel B – Apply a signal to
J2 from a 50Ω driver. Filters are required for data sheet
performance.
J3:
DEV
CLK
–
–
Encode clock input for single-ended
clocks – By default the DC1974 is defined to accept a
single-ended clock signal on J3. It can be modified to ac-
cept a differential clock signal through J3 and J4. Some
component changes are required, see the encode clock
section for more information.
J4:
DEV
CLK
+ – Encode clock input for differential sig-
nals – By default the DC1974 is defined to accept a
single-ended clock signal on J3. It can be modified to
accept a differential clock signal through J3 and J4. Some
component changes are required, see the encode clock
section for more information.
J5 and J6:
ADC_SYS_REF – JESD204B Subclass 1 only –
When testing the ADC in subclass 1 operation a SYS_REF
input is required to synchronize the ADC and FPGA. Apply
a SYS_REF signal to this input from a SYS_REF driver
board. This input drives the SYS_REF of the ADC.
J11 and J12:
FPGA_SYS_REF – JESD204B Subclass 1
only – When testing the ADC in subclass 1 operation a
SYS_REF input is required to synchronize the ADC and
FPGA. Apply a SYS_REF signal to this input from a SYS_REF
driver board. This input drives the SYS_REF of the FPGA.
J7 and J8:
FPGA_GBT_REF – This is an optional reference
port for the FPGA. It is used for testing purposes only. In
the default configuration these SMAs are not used.
J9 and J10:
FPGA_CLK – This is an optional clock input
port for the FPGA. It is used for testing purposes only. In
the default configuration these SMAs are not used.
TURRETS
V+:
Positive supply voltage for the ADC and digital
logic – This voltage feeds a regulator that supplies the
proper voltages for the ADC and buffers. The voltage range
for this turret is 4V to 6V. The supply should be able to
deliver 700mA of current.
SENSE:
Optional reference voltage – This pin is connected
directly to the SENSE pin of the ADC. Connecting SENSE
to VDD selects the internal reference and a ±0.66V input
range. The same input voltage range can be achieved
by applying an external 1.25V reference to SENSE. If no
external voltage is supplied this pin will be pulled up to
VDD through a 1k pull-up resistor.
1.8V OUT:
Optional 1.8V turret – This pin is connected
directly to the VDD pin of the ADC. It requires a supply that
can deliver up to 500mA. Driving this pin will shutdown the
on board regulator. It can also be a test point to measure
the voltage at the output of the regulators.
GND:
Ground Connection – This demo board only has a
single ground plane. This turret should be tied to the GND
terminal of the power supply being used.
JUMPERS:
JP1 EEPROM:
EEPROM write protect. For factory use only.
Should be left in the enable (PROG) position.
JP2 SYNC:
This jumper is provided to manually force the
SYNC~ signal of the ADC to a known value. By default,
the resistors connecting this jumper are removed. If R20
and R21 are installed the SYNC jumper can be used to
force SYNC~ high or low depending on the position of the
jumper. Position 0 is for low and 1 is for high.
