THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
A-MDMU
B-MDQL2
B-MDQU2
B-MA10
B-MBA1
A-MWEB
C1243
0.1uF
C1219
0.1uF
A-MA7
B-MA1
C1229
0.1uF
R1225
1K
1%
B-MA10
C1218
0.1uF
A-MDQL5
B-MA6
C1210
0.1uF
B-MA3
R1228
1K
1%
B-MA12
B-MDQU4
A-MBA2
C1223
0.1uF
C1230
0.1uF
A-MCASB
A-MA8
C1211
0.1uF
A-MDQSU
A-MA12
B-MDML
C1236
0.1uF
C1214
0.1uF
A-MDQL7
A-MA14
B-MDQL4
A-MDQL2
R1236
56
A-MDQL0
B-MDQU3
A-MODT
B-MVREFDQ
C1227
0.1uF
B-MA2
A-MCASB
A-MA2
B-MCKB
B-MDQSL
B-MODT
A-MDQU7
A-MA1
B-MA11
A-MDQL0
C1233
0.1uF
B-MDQL1
L1202
BLM18PG121SN1D
B-MDQSLB
C1208
0.1uF
A-MDQL2
C1207
0.1uF
B-MDQSUB
A-MA3
B-MDQL5
C1201
0.1uF
B-MA2
A-MDQL3
AVDD_DDR0
A-MDQU0
R1226
240
1%
B-MVREFCA
B-MDQSUB
B-MRESETB
A-MA14
A-MDQL1
C1202
1000pF
B-MBA0
A-MDQSLB
B-MDQU1
C1212
0.1uF
B-MCASB
B-MDQU3
B-MA13
B-MDQU7
AVDD_DDR1
A-MA4
AVDD_DDR1
A-MRESETB
C1239
0.1uF
C1224
0.1uF
B-MDQU1
A-MDQL4
A-MDML
AVDD_DDR0
C1249
1000pF
R1201
1K
1%
C1241
0.1uF
A-MVREFDQ
A-MRESETB
AVDD_DDR1
L1203
BLM18PG121SN1D
A-MCKB
A-MDQU7
A-MODT
A-MA5
C1220
0.1uF
A-MDQU4
B-MCK
B-MDML
C1237
0.1uF
R1237
56
C1216
0.1uF
B-MRESETB
A-MCKE
A-MDQL3
B-MDQU5
B-MDQL3
C1247
1000pF
B-MA14
A-MDMU
B-MDQL7
A-MA13
B-MDQU4
A-MVREFCA
C1213
0.1uF
B-MA11
R1232
10K
C1206
0.1uF
B-MA8
R1202
1K
1%
B-MODT
B-MDQU6
B-MA9
A-MBA2
R1238
56
B-MDQL0
A-MDQL4
C1252
10uF
10V
OPT
H5TQ1G63DFR-H9C
IC1201
EAN61828901
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
A-MDQU2
AVDD_DDR1
B-MDMU
A-MBA1
A-MDQSLB
R1205
1K
1%
A-MDQU2
C1250
0.1uF
B-MWEB
B-MDQSL
B-MBA0
AVDD_DDR0
B-MA1
+1.5V_DDR
+1.5V_DDR
C1242
0.1uF
R1203
240
1%
A-MDQSU
R1231
10K
C1235
0.1uF
A-MBA0
A-MDQU1
B-MA14
A-MDQU5
A-MA5
A-MRASB
B-MDQU0
B-MDQSU
A-MDQU1
A-MDQSL
B-MDQL3
A-MDQSUB
B-MDQSU
C1238
0.1uF
B-MBA2
A-MA9
A-MA9
B-MDQL2
C1221
0.1uF
B-MWEB
R1235
56
A-MDQSL
C1231
0.1uF
A-MDQU3
B-MBA2
C1204
1000pF
B-MDMU
A-MCKE
A-MVREFDQ
B-MA3
B-MA0
B-MDQL1
A-MDML
R1224
1K
1%
A-MA10
B-MDQL6
A-MA10
A-MDQU0
B-MA4
AVDD_DDR1
C1251
10uF
OPT
A-MA4
B-MDQU7
B-MA8
B-MDQL6
B-MBA1
A-MA13
A-MBA1
B-MDQL0
A-MBA0
A-MDQU3
A-MA11
A-MDQL6
B-MDQSLB
B-MDQU6
B-MCKB
A-MCK
A-MDQU6
B-MCK
A-MA2
B-MDQU0
B-MA9
A-MA12
A-MDQSUB
AVDD_DDR0
C1203
0.1uF
B-MVREFDQ
R1227
1K
1%
C1228
0.1uF
A-MWEB
C1248
0.1uF
B-MCASB
C1222
0.1uF
C1215
0.1uF
A-MA8
B-MA6
B-MVREFCA
B-MDQL5
B-MCKE
B-MCKE
A-MRASB
A-MVREFCA
A-MDQL5
C1205
10uF
B-MA7
A-MA0
A-MDQU4
C1232
0.1uF
A-MDQU5
B-MA13
C1246
10uF
A-MDQL7
B-MA5
B-MDQL4
A-MDQU6
B-MA7
A-MA6
H5TQ1G63DFR-H9C
IC1202
EAN61828901
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
B-MRASB
A-MA0
C1217
0.1uF
C1244
0.1uF
AVDD_DDR0
A-MDQL6
C1245
0.1uF
A-MA3
A-MCKB
A-MA7
A-MDQL1
C1234
0.1uF
A-MA11
A-MA1
A-MA6
B-MA12
B-MDQL7
B-MA5
B-MA0
B-MA4
A-MCK
B-MRASB
R1204
1K
1%
B-MDQU2
B-MDQU5
C1209
0.01uF
C1240
0.01uF
IC101
LGE2111A-W1 [MULTI]
A_DDR3_A[0]
A11
A_DDR3_A[1]
C14
A_DDR3_A[2]
B11
A_DDR3_A[3]
F12
A_DDR3_A[4]
C15
A_DDR3_A[5]
E12
A_DDR3_A[6]
A14
A_DDR3_A[7]
D11
A_DDR3_A[8]
B14
A_DDR3_A[9]
D12
A_DDR3_A[10]
C16
A_DDR3_A[11]
C13
A_DDR3_A[12]
A15
A_DDR3_A[13]
E11
A_DDR3_A[14]
B13
A_DDR3_BA[0]
F13
A_DDR3_BA[1]
B15
A_DDR3_BA[2]
E13
A_DDR3_MCLK
C17
A_DDR3_MCLKZ
A17
A_DDR3_MCLKE
B16
A_DDR3_ODT
E14
A_DDR3_RASZ
B12
A_DDR3_CASZ
A12
A_DDR3_WEZ
C12
A_DDR3_RESET
F11
A_DDR3_DQSL
B19
A_DDR3_DQSLB
C18
A_DDR3_DQSU
B18
A_DDR3_DQSUB
A18
A_DDR3_DQML
E15
A_DDR3_DQMU
A21
A_DDR3_DQL[0]
D17
A_DDR3_DQL[1]
G15
A_DDR3_DQL[2]
B21
A_DDR3_DQL[3]
F15
A_DDR3_DQL[4]
B22
A_DDR3_DQL[5]
F14
A_DDR3_DQL[6]
A22
A_DDR3_DQL[7]
D15
A_DDR3_DQU[0]
G16
A_DDR3_DQU[1]
B20
A_DDR3_DQU[2]
F16
A_DDR3_DQU[3]
C21
A_DDR3_DQU[4]
E16
A_DDR3_DQU[5]
A20
A_DDR3_DQU[6]
D16
A_DDR3_DQU[7]
C20
B_DDR3_A[0]
B23
B_DDR3_A[1]
D25
B_DDR3_A[2]
F22
B_DDR3_A[3]
G22
B_DDR3_A[4]
E24
B_DDR3_A[5]
F21
B_DDR3_A[6]
E23
B_DDR3_A[7]
D22
B_DDR3_A[8]
D24
B_DDR3_A[9]
D21
B_DDR3_A[10]
C24
B_DDR3_A[11]
C25
B_DDR3_A[12]
F23
B_DDR3_A[13]
E21
B_DDR3_A[14]
D23
B_DDR3_BA[0]
G20
B_DDR3_BA[1]
F24
B_DDR3_BA[2]
F20
B_DDR3_MCLK
G25
B_DDR3_MCLKZ
G23
B_DDR3_MCLKE
F25
B_DDR3_ODT
D20
B_DDR3_RASZ
B25
B_DDR3_CASZ
B24
B_DDR3_WEZ
A24
B_DDR3_RESET
E20
B_DDR3_DQSL
K24
B_DDR3_DQSLB
K25
B_DDR3_DQSU
J21
B_DDR3_DQSUB
J20
B_DDR3_DQML
H24
B_DDR3_DQMU
L20
B_DDR3_DQL[0]
L23
B_DDR3_DQL[1]
J24
B_DDR3_DQL[2]
L24
B_DDR3_DQL[3]
J23
B_DDR3_DQL[4]
M24
B_DDR3_DQL[5]
H23
B_DDR3_DQL[6]
M23
B_DDR3_DQL[7]
K23
B_DDR3_DQU[0]
G21
B_DDR3_DQU[1]
L22
B_DDR3_DQU[2]
H22
B_DDR3_DQU[3]
K20
B_DDR3_DQU[4]
H20
B_DDR3_DQU[5]
L21
B_DDR3_DQU[6]
H21
B_DDR3_DQU[7]
K21
DDR_256
CLose to DDR3
Close to DDR Power Pin
CLose to Saturn7M IC
CLose to DDR3
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
CLose to Saturn7M IC
DDR3 1.5V By CAP - Place these Caps near Memory
6
20120221
5
LM1_HW600G
Copyright
©
2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание PB60G
Страница 1: ...MARQUE LG REFERENCE PB60G CODIC 3661660 ...
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