LG LG-P500, Руководство по обслуживанию

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3. TECHNICAL BRIEF
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3.4 GPS RECEIVER
The GPS receiver input employs a single-ended connection realized by this pin. The GPS input is routed from
the GPS antenna switch, through a band pass filter and then an impedance transformer circuit that optimally
matches the impedance looking into the GPS LNA. The impedance transformer circuit topology is shown in
Figure 1-6.
[Figure 1.6] GPS Input Network Topology
3.5 LO GENERATION and DISTRIBUTION CIRCUIT
The integrated LO generation and distribution circuits are driven by internal VCOs to support various modes
to yield highly flexible quadrature LO outputs that drive all GSM/EDGE, UMTS band and GPS up-converters
and down-converters; with the help of these LO generation and distribution circuits, true zero-IF architecture
is employed in all GSM and UMTS band receivers and transmitters to translate the signal directly from RFto-
baseband and from baseband-to-RF. Two fully functional fraction-N synthesizers, including VCOs and loop
filters, are integrated within the RTR6285 IC. In addition, the RTR6285 has a third synthesizer used for GPS
operation. The first synthesizer (PLL1) in the RTR6285 creates the transceiver Los that support the UMTS
transmitter, and all four GSM band receivers and transmitters including: GSM850, GSM900, GSM1800, and
GSM1900. The second synthesizer (PLL2) in the RTR6285 IC provides the LO for the UMTS primary receiver.
For the RTR6285 IC only, the second synthesizer also provides the LO for the secondary UMTS receiver. The
third synthesizer (PLL3), only in the RTR6285 IC, provides the LO for the GPS receiver. An external TCXO input
signal is required to provide the synthesizer frequency reference to which the PLL is phase and frequency
locked. The RTR6285 ICs integrate most of the PLL loop filter components on-chip except for three off-chip
loop filter-series capacitors, which significantly reduces off-chip component requirement. With the
integrated fractional-N PLL synthesizers, the RTR6285 ICs have the advantage of more flexible loop
bandwidth control, fast lock time, and low-integrated phase error.