6. BLOCK DIAGRAM
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Copyright © 011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
EBI2_DATA[15:0]
D2[15:0]
OE2/, WE2/
EBI2_OE_N, WE_N
EBI2_CS0_N
NAND_CS/
NAND_UB2/
NAND_LB2/
NAND_WP/
NAND READY/
EBI2_UB_N
EBI2_LB_N
EBI1_RESOUT
EBI2 BUSY0 N
NAND 4Gb
GPIO_51~54
MICRO_SD_DATA[3:0]
MICRO_SD_CMD
MICRO_SD_CLK
MICRO SD DETECT
GPIO_56
GPIO55
tzt^YY^
_
/
EBI2_BUSY0_N
A1[13:0]/
D1[31:0]/
SDRAM_CLK
SDRAM CKE[1:0]
EBI1_ADR[13:0]
EBI1_DQ[31:0]
EBI1_DCLK
EBI1 CKE0
MICRO_SD_DETECT
GPIO_41
SDRAM_CKE[1:0]
SDRAM_CS[1:0]/
SDRAM_RAS/
SDRAM_CAS/
SDRAM_WE/
SDRAM_DQM[3:0]
DDR 4Gb
SDRAM_DQS[3:0]
EBI1_CKE0
EBI1_CS0_N
EBI1_RAS_N
EBI1_CAS_N
EBI1_WE_N
EBI1_DM_[3:0]
EBI1 DQS [3:0]
EBI1_DQS_[3:0]
SDRAM_BA[1:0]
SDRAM_CLK/
EBI1_DCLKB
EBI1_BA_[1:0]
t{Y`j[n`]thhwjqh
t{Y`j[n`]thhwjqh
UNIVA(E510) Block Diagram _ MEMORY