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Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. CIRCUIT DIAGRAM
+1V8_VREG_L6
R3200
DNI
Fiducial1
1
K4E2E304EE-AGCE
U3000
DNI
R3201
DNI
R3202
DNI
R3204
0.1u
C3204
NC_INDEX
RFU7
NC59
DAT0
NC60
DAT1
NC61
DAT2
NC62
DAT3
NC63
DAT4
NC64
DAT5
DS
DAT6
NC66
DAT7
NC67
NC68
CLK
NC69
NC70
CMD
NC71
VSS1
VDDI
NC73
VCCQ1
NC74
VCCQ2
NC75
VCCQ3
NC76
VCCQ4
NC77
VCCQ5
NC78
VCC1
RSTN
VCC2
RFU8
VCC3
RFU9
VCC4
RFU10
NC83
VSSQ5
NC84
VSS4
NC85
VSS5
NC86
VSS6
NC87
VSS7
NC88
VSSQ1
NC89
VSSQ2
NC90
VSSQ3
NC91
VSSQ4
NC92
NC93
NC1
NC94
NC2
NC95
VSS2
NC96
RFU1
NC97
NC5
NC98
NC6
NC99
NC7
NC100
NC8
NC101
NC9
NC102
NC10
NC103
NC11
NC104
NC12
NC105
NC13
NC106
NC14
NC107
NC15
NC108
NC16
NC109
NC17
NC110
NC18
NC111
NC19
NC112
NC20
NC113
NC21
NC114
NC22
NC115
NC3
RFU5
NC24
NC117
NC25
NC118
NC26
RFU6
NC27
NC120
NC28
NC121
NC29
NC122
NC30
NC123
NC31
NC32
NC33
NC34
NC3
5
NC36
NC37
NC38
NC39
NC40
RFU2
RFU3
VSF
3
VSF
2
NC45
NC46
NC47
NC48
NC49
NC50
VSF
1
NC52
NC5
3
NC54
NC55
NC56
RFU4
THGBMBG7D2KBAIL
U3200
G3
G2
G1
F1
4
F1
3
F1
2
F1
0
F3
F2
F1
E1
4
E1
3
E1
2
E1
0
E9
E8
E5
E3
E2
E1
D14
D13
D12
D3
D2
D1
C14
P14
C13
P13
C12
P12
C11
P11
C10
P10
C9
P9
C8
P8
C7
P7
C5
P2
C3
P1
C1
N14
B14
N13
B13
N12
B12
N11
B11
N10
B10
N9
B9
N8
B8
N7
B7
N6
B1
N3
A14
N1
A13
M14
A12
M13
A11
M12
A10
M11
A9
M10
A8
M9
A7
M8
A6
M7
A2
M3
A1
M2
M1
P6
L14
P4
L13
N5
L12
N2
L3
K8
L2
H10
L1
G5
K14
E7
K13
C4
K12
K10
K9
K7
J10
K6
F5
K5
E6
K3
P5
K2
P3
K1
N4
J1
4
M4
J1
3
C6
J12
C2
J5
J3
M5
J2
J1
M6
H14
H13
B6
H12
B5
H5
B4
H3
B3
H2
B2
H1
A5
G14
A4
G13
A3
G12
G10
D4
+1V8_VREG_L6
C3200
2.2u
2.2u
C3205
C3202
DNI
DNI
C3203
R3211
DNI
10K
R3208
0.1u
C3201
0.1u
C3206
+1V8_VREG_L6
DNI
R3210
DNI
R3205
+2V95_VREG_L17
R3206
DNI
DNI
R3207
R3203
DNI
eMMC_CLK
MSM_RESOUT_N
eMMC_CMD
eMMC_DATA_7
eMMC_DATA_6
eMMC_DATA_5
eMMC_DATA_4
eMMC_DATA_3
eMMC_DATA_2
eMMC_DATA_1
eMMC_DATA_0
eMMC_DS
< 3-2-3-2-1_eMMC_5_0_16Gbyte_Toshiba >
Rev_0.3
OPEN NET(MSM8926 - eMMC 4.5 )
Pull-down resistance for Data Strobe (HS400 Mode)
If there are removed DNI, add TP. (over 0.5mm)
For V5.0
Rank 1 : 4Gb (x32)
Rank 0 : 4Gb (x16) + 4Gb (x16)
POP_12Gb 168ball 800MHz (23nm , 4Gb x 3) , SS
8GBIT
H9TKNNN8JDAPLR-NGH
EAN62949701_POP
Rev_1.0
< 3-1-2-3-1_LPDDR2_PoP_8Gbit_SK_Hynix >
POP_8Gb 168ball 533MHz (38nm, 4Gb x 2), Hynix
<LPDDR3_POP_12Gbit_SS EAN63445801>