3.11.10 UART
The MSM6280 device employs three UARTs. UART1 has dedicated pins while UART2 and UART3
share multiplexed pins.
3.11.11 USB
The MSM6280 device integrates a universal serial bus (USB) controller that supports both
unidirectional and bidirectional transceiver interfaces. The USB controller acts as a USB peripheral
communicating with the USB host. MSM6280 supports the 3-wire USB functionality.
3.12 External memory interface
The MSM6280 device was designed to provide two distinct memory interfaces. EBI1is used to support
high-speed synchronous memory devices. EBI2 is used to support slower asynchronous devices such
as LCD and NAND Flash.
■
EBI1 Features
- 32-bit SDRAM (low power SDRAM)
- The MSM6280 device supports only 32-bit SDRAM. NOR/PSRAM configurations are not
supported. The reason that only 32-bit SDRAM is supported on the MSM6280 device is that when
higher speed HSDPA (7.2 Mbps) is implemented, the ARM will be clocked at 270 MHz and the bus
at 90 MHz. QUALCOMM at this time guarantees 3.6 and 7.2 Mbps HSDPA performance with this
memory configuration. HSDPA performance on the MSM6280 device with NOR/PSRAM parts
cannot be guaranteed at this time. There could also be potential MIPs issues for HSDPA with
NOR/PSRAM and 16-bit SDRAM. Therefore, we strongly recommend customers to use 32-bit
SDRAM in their designs.
■
EBI2 Features
- Support for asynchronous flash (16-bit and 8-bit). Page mode is not supported.
Programmable wait states for access, hold, and recovery for all chip-selects.
- Interface support for byte addressable 16-bit devices (UB_N and LB_N signals)
- Support for 8-bit and 16-bit wide NAND Flash
- Support of four general-purpose chip-selects. Two of these chip-selects can be configured as
NAND chip-selects.
- Support for parallel, port-mapped LCD interfaces (Intel and Motorola timing), (18- bit, 16-bit, and 8-
bit)
- Support for system word, Hword, and byte accesses to 16-bit and 8-bit wide devices on all chip-
selects (bus sizing supported for all interfaces with the exception of NAND)
- Support for memory accesses (with exception of NAND) by SYS AHB and DMA AHB bus. NAND
is accessed through a special controller
LGE Internal Use Only
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
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