LG KP500, Руководство по обслуживанию

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3. TECHNICAL BRIEF
LGE Internal Use Only Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3.6 Memory
2Gbit NAND & 1Gbit DDRSDRAM employed on KF500 with 8 & 16 bit parallel data bus thru ADD(0) ~
ADD(29). The 1Gbit Nand Flash memory with DDRAM stacked device family offers multiple high-
performance solutions.
SD_1V8
R
2
0
2
0
.1
u
SD_1V8
1
0
K
C
2
1
4
0
.1
u
C
2
2
4
C
2
2
2
0
.1
u
C
2
1
8
0
.1
u
3
.3
K
R
2
0
3
TP201
TP202
TP205
TP200
0
.1
u
C
2
2
0
C
2
2
3
0
.0
1
u
C
2
1
9
0
.0
1
u
C
2
2
5
0
.0
1
u
C
2
1
5
0
.0
1
u
SD_1V8
TP204
N3
_WP
P8
VDDQ2
C5
VSS1
C9
VSS2
G2
VSS3
H10
VSS4
P7
VSS5
VSS6
P9
P5
VSSQ
E6
_CAS
G3
_CE
C6
_CLK
_CS
D5
F6
_RAS
F3
_RE
D6
_WED
M3
_WEN
N
C
6
6
T
2
N
C
6
7
T
3
T
1
0
N
C
6
8
N
C
6
9
T
1
1
B
1
N
C
7
N
C
7
0
T
1
2
B
2
N
C
8
B
3
N
C
9
E3
R__B
K7
UDQM
L7
UDQS
H2
VCCN1
C4
VDD1
C8
VDD2
P6
VDD3
P4
VDDQ1
L
2
N
C
5
1
N
C
5
2
M
2
N
C
5
3
N
2
N
C
5
4
P
1
P
2
N
C
5
5
P
3
N
C
5
6
N
C
5
7
P
1
1
P
1
2
N
C
5
8
Q
1
N
C
5
9
A
1
2
N
C
6
Q
2
N
C
6
0
N
C
6
1
Q
3
N
C
6
2
Q
1
0
N
C
6
3
Q
1
1
N
C
6
4
Q
1
2
N
C
6
5
T
1
N
C
3
7
J
4
J
5
N
C
3
8
N
C
3
9
J
6
N
C
4
A
1
0
N
C
4
0
J
7
N
C
4
1
J
8
J
9
N
C
4
2
J
1
0
N
C
4
3
J
1
1
N
C
4
4
K
2
N
C
4
5
K
4
N
C
4
6
K
5
N
C
4
7
K
8
N
C
4
8
N
C
4
9
K
9
A
1
1
N
C
5
K
1
0
N
C
5
0
N
C
2
2
H
1
1
F
2
N
C
2
3
N
C
2
4
F
9
N
C
2
5
G
6
N
C
2
6
G
9
N
C
2
7
G
1
0
N
C
2
8
H
3
N
C
2
9
H
4
A
3
N
C
3
N
C
3
0
H
5
H
6
N
C
3
1
H
7
N
C
3
2
H
8
N
C
3
3
N
C
3
4
H
9
J
2
N
C
3
5
N
C
3
6
J
3
K6
LDQM
LDQS
L6
N
C
1
A
1
B
1
0
N
C
1
0
B
1
1
N
C
1
1
N
C
1
2
B
1
2
N
C
1
3
C
1
N
C
1
4
C
2
C
3
N
C
1
5
N
C
1
6
C
1
1
N
C
1
7
C
1
2
D
1
N
C
1
8
D
2
N
C
1
9
A
2
N
C
2
D
3
N
C
2
0
N
C
2
1
E
2
P10
I_O0
N10
I_O1
L11
I_O10
I_O11
K11
I_O12
G11
I_O13
F11
E11
I_O14
D11
I_O15
M10
I_O2
L10
I_O3
F10
I_O4
E10
I_O5
D10
I_O6
I_O7
C10
I_O8
N11
I_O9
M11
DQ0
L4
DQ1
M4
DQ10
L8
M8
DQ11
N8
DQ12
L9
DQ13
M9
DQ14
N9
DQ15
DQ2
N4
DQ3
L5
M5
DQ4
DQ5
N5
DQ6
M6
N6
DQ7
DQ8
M7
DQ9
N7
A12
E7
A13
E9
A2
F4
A3
G4
A4
G8
A5
F8
A6
E8
D8
A7
A8
D9
A9
G7
L3
ALE
BA0
E5
BA1
F5
CKE
D7
K3
CLE
CLK
C7
U201
H8BCS0SI0MAP_56M
EUSY0347503
A0
D4
A1
E4
A10
G5
A11
F7
0
.1
u
C
2
1
6
0
.0
1
u
C
2
1
7
TP203
0
.0
1
u
C
2
2
1
) 7 1 ( D D A
1 A B
) 7 ( A T A D
) 6 ( A T A D
) 5 ( A T A D
) 4 ( A T A D
) 3 ( A T A D
) 2 ( A T A D
) 1 ( A T A D
) 0 ( A T A D
) 9 2 : 6 1 ( D D A
) 5 1 ( A T A D
) 4 1 ( A T A D
) 3 1 ( A T A D
) 2 1 ( A T A D
) 1 1 ( A T A D
) 0 1 ( A T A D
) 9 ( A T A D
) 8 ( A T A D
P D C F
1 C B _
S Q D U
S A C _
S C _ D N A N _
I K L C D S
S C _ M A R _
S A R _
D R _
R W _
R W _
P W _
) 8 ( D D A
) 9 ( D D A
) 0 1 ( D D A
) 1 1 ( D D A
) 2 1 ( D D A
) 3 1 ( D D A
) 4 1 ( D D A
) 5 1 ( D D A
) 5 1 : 0 ( A T A D
) 6 1 ( D D A
0 A B
E K C
O K L C D S
0 C B _
S Q D L
) 6 2 ( D D A
) 7 2 ( D D A
) 8 2 ( D D A
) 9 2 ( D D A
) 6 1 ( D D A
) 7 1 ( D D A
) 5 1 : 0 ( D D A
) 0 ( D D A
) 1 ( D D A
) 2 ( D D A
) 3 ( D D A
) 4 ( D D A
) 5 ( D D A
) 6 ( D D A
) 7 ( D D A
) 8 1 ( D D A
) 9 1 ( D D A
) 0 2 ( D D A
) 1 2 ( D D A
) 2 2 ( D D A
) 3 2 ( D D A
) 4 2 ( D D A
) 5 2 ( D D A
Figure 9 Flash memory & DDR RAM MCP circuit diagram