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Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. BB Circuit Technical brief
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2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
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Shared Memory Block
1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite®.
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Controller Bus system
The processor cores and their peripherals are connected by powerful buses.
- Multi-layer AHB for connecting the ARM and the other master capable building blocks with the
internal and external memories and with the peripheral buses.
- An FPI-Bus for connecting GSM peripherals, called hereafter FPI3 bus.
- A controller FPI bus for connecting the low performance controller peripherals such as keypad
etc. called hereafter fPI2 bus.
- FPI2 and FPI3 are connected asynchronously to the AHB buses. 1 DMA controller with
8channels offloads the controller from data transfers.
- 2 AHB Lite buses for connecting multi-media and high performance peripherals, called
AHB_PER1 and AHB_PER2 hereafter. These peripheral buses are connected to the multi-layer
AHB ‘backbone’ by asynchronous, burst capable AHB2AHB bridges which are shared between
accessing masters.
- The DMA controller is enabled to access AHB_PER1 by use of its first master interface and
AHB_PER2 by its second master interface.
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TEAKLite® Bus System
- 1 TEAKLite® data bus for connecting the TEAKLite® data memory and the TEAKLite® peripherals.
Also the data bus is connected into the controller system via shared RAMs to the FPI3 bus.
- 1 TEAKLite® program bus for connecting the TEAKLite® program memory to the TEAKLite®.
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Clock system
The clock system allows widely independent selection of frequencies for the essential parts of the S-
GOLD®3H. Thus power consumption and performance can be optimized for each application.
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Functional Hardware block
- CPU and DSP Timers
- MOVE coprocessor performing motion estimation for video encoding algorithms
(H.263, MPEG-4)
- Programmable PLL with four additional phase shifters for system clock generation
- GSM Timer Module that off-loads the CPU from radio channel timing
- GMSK / 8-PSK Modulator according to GSM-standard 05.04 (5/2000)
· GMSK Modulator: gauss-filter with B*T=0.3
· EDGE Modulator: 8PSK-modulation with linearized GMSK-Pulse-Filter
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