LG KF350, Руководство по обслуживанию

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- 115 -
PWR
URXD
UTXD
3G 2.5G
GND
RX
TX
VCHAR
ON_SW
VBAT
UART
10
Large Block : R113 -> NA, R110 -> 1K
1 2
F
D
E
F
G
4 5
H
10 11 12
2 3
D
1G NAND(Large Block x16bit) +512M DDR SDRAM
B
E
A
11
3 6
C
8
8 9
C
Small Block : R113 -> 10K, R110 -> NA
4 5
Boot Mode
BASE BAND PROCESSOR
CAL&AUTO POINT
12 7
H
7
G
ON BOARD ARM9 JTAG & ETM INTERFACE
B
6
A
9 1
1K
R111
OJ102 OJ101
UT101
12
CTS
10
DSR
1
GND
4
NC1
NC2
7
8
NC3
NC4
9
ON_SW
5
RTS
11
2
RX
TX
3
VBAT
6
1V8_SD
C134
22p
0.1u
C136
0.1u
C128
2V5_VAUDB
VSSP_DIG4
VSSP_MEM_ETM1
U1 V2
VSSP_MEM_ETM2
W1
VSSP_MEM_ETM3 VSSP_MEM_ETM4
W10 K12
VSS_MAIN1 VSS_MAIN2
K11
VSS_MAIN3
K10 K9
VSS_MAIN4
K8
VSS_MAIN5
M11
VSS_MAIN6 VSS_MAIN7
M10
VSS_MAIN8
M9 M8
VSS_MAIN9
T12
VSS_PLL
AA14
VSS_RTC VDD_PLL
VDD_RTC
AA13
VMICN
U16 T15
VMICP
VREFN
P16
VREFP
R16
VSSA_BB
L15 U14
VSSA_BG
T14
VSSA_D VSSA_M
W15 R17
VSSA_VBR1
U17
VSSA_VBR2
N17
VSSA_VBT
H2
VSSP_DIG1 VSSP_DIG2
A7
VSSP_DIG3
J17 B10
VDDP_MEM_ETM3
Y1
VDDP_MEM_ETM4 VDDP_MEM_ETM5
P1 A13
VDDP_MMC
VDDP_SIM
K19
VDD_FUSE_FS
L2 J11
VDD_MAIN1
VDD_MAIN10
N9
VDD_MAIN2
J10 J9
VDD_MAIN3 VDD_MAIN4
L12
VDD_MAIN5
L11 L10
VDD_MAIN6 VDD_MAIN7
L9 L8
VDD_MAIN8
N10
VDD_MAIN9
W13
E2
VDDA_BB
P15
VDDA_BG
T13 T16
VDDA_D
U13
VDDA_M
T17
VDDA_VBR1 VDDA_VBR2
W19
VDDA_VBT
N18
VDDP_DIGA
F17 A5
VDDP_DIGB
VDDP_DIGC1
A16
VDDP_DIGC2
C17 B2
VDDP_DIGD VDDP_DIGE
H1
VDDP_MEM_ETM1
AA10
VDDP_MEM_ETM2
AA3 AA6
T_OUT4
T_OUT5
F12
B13
T_OUT6
C11
T_OUT7
T_OUT8
E12
C12
T_OUT9
USIF1_CTS_N
F4 E1
USIF1_RTS_N USIF1_RXD_MRST
F5 F3
USIF1_TXD_MTSR
F14
USIF2_CTS_N USIF2_RTS_N
G16 H19
USIF2_RXD_MRST USIF2_TXD_MTSR
J16
E3
USIF3_RXD_MRST
E4
USIF3_SCLK USIF3_TXD_MTSR
AA12 AA11
TRACEPKT3 TRACEPKT4
AA9 Y15
TRACEPKT5 TRACEPKT6
Y11 Y12
TRACEPKT7
TRACESYNC
AA7
E14
TRIG_IN
TRST_N
F13
B15
T_IN0
C13
T_IN1
E13
T_OUT0
T_OUT1
B14
T_OUT10
B12
F11
T_OUT2
T_OUT3
A15
E11
RF_STR1
RSTOUT_N
H18
RTCK
F16
RTC_OUT
Y14
SPCU_RC_OUT0
H17
SPCU_RQ_IN0
J18
J19
SPCU_RQ_IN1
G18
SPCU_RQ_IN2
SWIF_TXRX
H15
C16
TCK
B18
TDI
TDO
A18
TMS
C15
U11
TRACECLK
TRACEPKT0
AA8 Y10
TRACEPKT1 TRACEPKT2
Y17
W16
M_7
M_8
AA17
Y16
M_9
N11
NC
OSC32K
AA15
K16
PAOUT11
PAOUT12
M12
PIPESTAT0
Y8
T10
PIPESTAT1
Y9
PIPESTAT2
Y13
PM_INT
RESET_N
W14
RF_CLK
B17
RF_DATA
E15
RF_STR0
D17
D18
MMCI1_DAT0
C9
MMCI1_DAT1
F10
MMCI1_DAT2
MMCI1_DAT3
A14
MMCI2_CLK
F6
D3
MMCI2_CMD
D2
MMCI2_DAT0
MON1
B16
MON2
C10
M_0
W18
V17
M_1
M_10
U15
M_2
Y19
Y18
M_3
M_4
W17
AA18
M_5
M_6
MEM_CS3_N
MEM_CSA0_N
U3
MEM_CSA1_N
U4
MEM_CSA2_N
T6
MEM_CSA3_N
T5
Y7
MEM_RAS_N
L1
MEM_RDN
Y2
MEM_SDCLKO
K2
MEM_WAITN
R3
MEM_WRN
N19
MICN1 MICN2
M18
MICP1
P19 M17
MICP2
MMCI1_CLK
A12
MMCI1_CMD
E10
B11
MEM_AD6
N2
MEM_AD7
MEM_AD8
J4
MEM_AD9
K4
MEM_ADVN
M1
MEM_BC0_N
AA2
V3
MEM_BC1_N
U5
MEM_BC2_N
MEM_BC3_N
Y4
W3
MEM_BFCLKO1
MEM_BFCLKO2
Y3
MEM_CAS_N
W8
MEM_CKE
U10
R2
MEM_CS0_N
MEM_CS1_N
P3
N3
MEM_CS2_N
N4
MEM_A6
MEM_A7
U7
Y5
MEM_A8
AA5
MEM_A9
MEM_AD0
M2
L3
MEM_AD1
K5
MEM_AD10
MEM_AD11
L4
R1
MEM_AD12
MEM_AD13
M5
M4
MEM_AD14
MEM_AD15
P4
MEM_AD2
J3
L5
MEM_AD3
MEM_AD4
M3
N1
MEM_AD5
P2
MEM_A15
MEM_A16
V1
N5
MEM_A17
U2
MEM_A18
W2
MEM_A19
MEM_A2
T8
MEM_A20
R5
T1
MEM_A21
MEM_A22
R4
MEM_A23
T2
P5
MEM_A24
MEM_A25
T3
MEM_A26
T4
MEM_A3
U6
W5
MEM_A4
MEM_A5
AA4
T7
H3
KP_IN3
H5 J2
KP_IN4 KP_IN5
J1
KP_IN6
K3
KP_OUT0
G4 G3
KP_OUT1
F1
KP_OUT2 KP_OUT3
G5
U8
MEM_A0
W4
MEM_A1
W6
MEM_A10
MEM_A11
T9
MEM_A12
W7
MEM_A13
Y6
MEM_A14
U9
W9
E16 D19
I2S1_CLK1
E18
I2S1_RX
E17
I2S1_TX I2S1_WA0
B19 G19
I2S2_CLK0
G15
I2S2_CLK1 I2S2_RX
F18
I2S2_TX
E19 F19
I2S2_WA0 I2S2_WA1
G17
IRDA_RX
G2
F2
IRDA_TX
IREF
R15
G1
KP_IN0
J5
KP_IN1 KP_IN2
R19 T18
EPPA11 EPPA12
T19
EPPA21
V18 V19
EPPA22 EPREF1
U18 U19
EPREF2
F26M
U12
AA16
F32K
FCDP_RBN
T11
W11
FWP
GUARD
J15
I2C1_SCL
C14 A17
I2C1_SDA
C19
I2C2_SCL I2C2_SDA
F15
I2S1_CLK0
A2
DIF_D6
B3 B4
DIF_D7 DIF_D8
C2
DIF_HD
C4 B1
DIF_RD
F8
DIF_RESET1
C7
DIF_RESET2 DIF_VD
D1
DIF_WR
C3
DSPIN0
H4
DSPIN1
K1 E6
DSPOUT1 EPN11
P17 P18
EPN12
R18
EPP11 EPP12
A10
A4
CIF_VSYNC
W12
CLKOUT0
B6
CLKOUT2
CORNER_A1
A1 A19
CORNER_A2
AA1
CORNER_AA1 CORNER_AA2
AA19
C5
DIF_CD
C1
DIF_CS1 DIF_CS2
E5 F7
DIF_D0 DIF_D1
C6
DIF_D2
B5 E7
DIF_D3
A3
DIF_D4 DIF_D5
M16
BB_QX
K15
K18
CC_CLK
CC_IO
H16
CC_RST
K17
CIF_D0
F9
CIF_D1
A11
A9
CIF_D2
C8
CIF_D3
B8
CIF_D4 CIF_D5
B9 A8
CIF_D6
E8
CIF_D7 CIF_HSYNC
E9
CIF_PCLK
B7
CIF_PD
A6
CIF_RESET
U102
PMB8877
C18
AFC
N16
AGND
L16
AUXGND
L17
AUXN1 AUXN2
L19
AUXP1
M19 L18
AUXP2
N15
BB_I
BB_IX
M15
BB_Q
1 2
1V8_SD
32.768KHz
X101
1u
0.1u
C131
C104
C6
_CK
G4
E9
_CS
E7
_RAS
E5
_RE
D6
_WE
_WED
F8
F5
_WP
1V8_SD
H2
VDD4
M2
VDDQ1
D2
VDDQ2
F2
VDDQ3
K2
C2
VSS1
F9
VSS2
VSS3
G2
N4
VSS4
VSS5
B5
VSS6
N5
N8
VSS7
VSSQ1
E2
J2
VSSQ2
VSSQ3
L2
F7
_CAS
_CE
B7
NC3
B9
NC4
E8 F6
NC5
G5
NC6
G6
NC7
H5
NC8 NC9
H6
R__B
E6
H3
UDQM
J3
UDQS
B6
VCC1
VCC2
N7
VCCQ
N6
B4
VDD1
G9
VDD2
VDD3
M7
K8
IO14
M8
IO15
IO2
J6
IO3
L6
J7
IO4
L7
IO5
IO6
J8
IO7
L8
IO8
K5
M5
IO9
G3
LDQM
F3
LDQS
NC1
B2
N2
NC10 NC11
N9
NC2
DQ13
M4
DQ14
DQ15
N3
C3
DQ2
DQ3
D4
DQ4
D3
DQ5
E4
E3
DQ6
DQ7
F4
DQ8
J4
K3
DQ9
J5
IO0
L5
IO1
K6
IO10
M6
IO11
K7
IO12
IO13
DNU1
DNU10
P9 P10
DNU11
DNU2
A9 A10
DNU3
B1
DNU4 DNU5
B10
DNU6
N1 N10
DNU7 DNU8
P1 P2
DNU9
DQ0
B3
DQ1
C4
DQ10
K4
L3
DQ11
DQ12
L4
M3
A11
G7
A12
C9
A2
B8
A3
M9
A4
A5
L9
K9
A6
J9
A7
H7
A8
A9
H8
D5
ALE
D7
BA0
BA1
D8
G8
CKE
C5
CLE
CLK
H4
A2
U101
K5E1H12ACM-D075
C7
A0
A1
C8
D9
A10
H9
1V8_SD
TP107
0.1u
C115
1000p
C137
2V5_VAUDA
FB101
TP103
VCHG
C116
0.1u
C123
0.1u
C109
0.1u 0.1u
C108
R113
DNI
C101
1u
0.1u
C126
10K
R112
0.1u
C119
R105 100K
C120
C133 220n
2V62_VIO
0.1u
2V11_RTC
2V9_SIM
TP102
17
18
19
20
21
22
23
24
G1 G2
G3 G4
14
15
2
3
4
5
6
7
8
9
16
25
26
27
28
29
30
CN101
1
10
11
12
13
VUSB_USB
C135
0.1u
22p
C102 C118
2V62_VIO
0.1u
C130
TP104
0.1u
C107
1u
C122
0.1u
C112
0.1u 0.1u
TP108
C110
R115
1.5K
C111
1V8_SD
TP106
R106
3300
0.1u
0.1u
C105
R103 390K
UART_TX
FB102
FB103
39p
C141
C125
0.1u
R114 22K
R108
10K
TP101
1V8_SD
RPWR
C132
0.1u
0.01u
C106
1.5K
R116
2V62_VIO
2V62_VIO
C124
1u
C113
0.1u
C114
0.1u
TP105
UART_RX
FB104
C129
0.1u
0.01u
C103
0.1u
C117
C127
0.1u
39p
R110
C139
1K
GND
1V8_SD
2V62_VIO
1V35_VPLL
VBAT
1
R101
C121
1u
39p
C138
2V9_VMME
C140
1V35_CORE
39p
MAIN_MIC_P
UART_RX
UART_TX
RPWRON_EN
TRIG_IN
DSR
VMIC_P
MAIN_MIC_N
HS_MIC_N HS_MIC_P
DATA(11)
DATA(12)
DATA(13)
DATA(14)
DATA(15)
DATA(10)
USB_DM
USB_DP
FLIP
_LED_RESET
LED_CNT
VMIC_N
FCDP
DATA(8)
DATA(9)
DATA(10)
DATA(11)
DATA(12)
DATA(13)
DATA(14)
DATA(15)
DATA(0)
DATA(1)
DATA(3)
DATA(4)
DATA(5)
DATA(6)
DATA(7)
DATA(2)
DATA(0:15)
DATA(8)
DATA(9)
ADD(21)
ADD(22)
ADD(23)
ADD(24)
ADD(25)
ADD(16:28)
DATA(0)
DATA(1)
DATA(2)
DATA(3)
DATA(4)
DATA(5)
DATA(6)
DATA(7)
ADD(0:15)
DATA(0:15)
ADD(16)
ADD(17)
ADD(26)
ADD(27)
ADD(28)
ADD(18)
ADD(19)
ADD(20)
ADD(14)
ADD(15)
_RAM_CS
ADD(29)
ADD(30)
CKE
_CAS
_RAS
SDCLKO
_WR
_BC0
_BC1
_NAND_CS
ADD(16)
ADD(17)
_RD
_WR
UDQS
SDCLKI
ADD(0)
ADD(1)
ADD(2)
ADD(3)
ADD(4)
ADD(5)
ADD(6)
ADD(7)
ADD(8)
ADD(9)
ADD(10)
ADD(11)
ADD(12)
ADD(13)
KEY_ROW5
JACK_TYPE
MMC_DETECT
I2S1_CLK
BT_LDO_EN
LDQS
TRACEPKT5
TRACEPKT6
TRACEPKT7
TRACECLK
PIPESTAT0
PIPESTAT1
PIPESTAT2
TRACESYNC
ADD(0:26)
ADD(26)
ADD(27)
ADD(28)
ADD(29)
ADD(30)
LDQS
UDQS
PA_LEVEL
DBB_INT
CIF_SCL CIF_SDA
BB_SND_R
TRSTn
TDI
TMS
TCK
RTCK
TDO
EXTRSTn
TRIG_IN
TRACEPKT0
TRACEPKT1
TRACEPKT2
TRACEPKT3
TRACEPKT4
KEY_COL3
RPWRON_EN
WDOG
KEY_EN
SDCLKI
MMC_CLK
MMC_CMD
MMC_D(0)
MMC_D(3)
VIB_EN
USB_SE0_VM
CIF_MCLK
UART_BT_CTS UART_BT_RTS
CIF_HSYNC
CIF_PCLK
CIF_PD
CIF_RESET CIF_VSYNC
USB_OEn
KEY_ROW0
KEY_COL2
LCD_ID
KEY_COL1
KEY_ROW1
KEY_ROW4
KEY_ROW2
KEY_ROW3
KEY_COL0
MMC_D(1)
VCXO_EN
VREFN
VREFN
SDCLKO
DIF_VSYNC
CHG_EN
CLK32K
_PPR
KEY_COL5
TMS
TRACECLK
TRACEPKT0 TRACEPKT1 TRACEPKT2 TRACEPKT3 TRACEPKT4 TRACEPKT5 TRACEPKT6 TRACEPKT7
TRACESYNC
TRSTn
TXON_PA
PA_BAND
FE1
PA_MODE
JACK_DETECT
UART_BT_RX
UART_RX
UART_BT_TX
MMC_D(2)
RF_TEMP
PIPESTAT0
PIPESTAT1
PIPESTAT2
PM_INT
_RESET
RF_CLK
RF_DA
RF_EN
RTCK
RTC_OUT
FE2
SCL
SDA
TCK
TDI
TDO
ADD(25)
_NAND_CS
_BC0
_BC1
FCDP
_CAS
CKE
_RAM_CS
_RD
_WR
EAR_N EAR_P
BB_SND_L
26MHZ_MCLK
I2S1_RX
I2S1_TX
I2S1_WA0
BT_INT
_EOC
BAT_ID
_DIF_WR
USB_DAT_VP
UART_TX
ADD(0)
ADD(1)
ADD(10)
ADD(5)
ADD(11)
ADD(6)
ADD(12)
ADD(7)
ADD(13)
ADD(8)
ADD(14)
ADD(9)
ADD(15)
ADD(16)
ADD(17)
ADD(18)
ADD(19)
ADD(2)
ADD(20)
ADD(21)
ADD(22)
ADD(23)
ADD(24)
ADD(3)
ADD(4)
CIF_D3 CIF_D4 CIF_D5 CIF_D6 CIF_D7
HOOK_DETECT
DIF_RD DIF_CD
DIF_MAIN_CS
DIF_D0 DIF_D1 DIF_D2 DIF_D3 DIF_D4 DIF_D5 DIF_D6 DIF_D7
_DIF_RESET
RPWRON_EN
UART_RX
DSR
UART_TX
VBAT
RESOURCE_CTRL
BT_RESETn
_RAS
I
IX
Q
QX
SIM_CLK
SIM_IO
SIM_RST
CIF_D0 CIF_D1 CIF_D2
7. CIRCUIT DIAGRAM
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Only for training and service purposes