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Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
LG Electronics
13/115
LGE Property
III. Technical brief
III-1 Baseband circuit
3.1 GT350 Functional Block diagram
The functional component arrangement is mentioned below diagram.
LGE Internal Use Only
GT350 BLOCK DIAGRAM
PMB6821(PM IC)
BB IC(PMB8877)
(2G NAND +
1G DDR SDRAM)
Charging IC
Ր
-SD
TRANSCEIVER
PMB6272
LMSP4DNA
BT/FM IC
(BCM20780)
Haptic Driver
LCD, 3.0”
262K TFT WQVGA
KEY PAD
KEY Back Light
Charge Pump
SD1 (1.35V)
SD2(1.8V)
SU1(5.6..25V)
VAUX (2.9V)
VIO(2.62V)
VSIM(2.9V)
VMME (2.9V)
VUMTS(2.85V)
VUSB(3.1V)
VVIB(2.8V)
VAUDIOa(2.5V)
VAUDIOb(2.5V)
VRF1(2.85V)
VRF2(1.53V)
VRF3(2.70V)
VPLL(1.35V)
VRTC(2.0V)
VAFC (2.65V)
VBAT
DCS/PCS
GSM850/900
FEM
PAM(SKY77344)
2M CAM
FE1 FE2
PA_MODE
PA_BAND
TXON_PA
PA_LEVEL
I/I_/Q/Q_
RF_EN
RF_CLK
RF_DA
26M_MCLK
26M_Crystal
ANT
BPF
BT ANT
FM ANT
UART
/
/
I2S
/
BT_CLK
ADD(0:29)
/
DATA(0:15)
/
32kHz
Headset Reciever(L/R)
MAIN MIC
FM RADIO
FM RADIO
AUIDO AMP
EPN11
EPP11
EPPA11
EPPA21
INM-
INM+
INL
INR
MAIN SPEAKER
OUT-
OUT+
MIC1(P/N)
MIC2(P/N)
VMICP/N
I2C
/
INL/R
t
p
l
y
iwhzz
w
y
l
T
h
t
w
Match
Match
Match
Match
Controller
Battery
CHG_EN
T_IN1
I2C1
/
(LED CTRL : 6 ea)
I2C2
/
SET/EN
VBAT
Power_KEY
COL
ROW
GPIO
2V11_RTC
2V11_RTC
B/UP BAT.
I2C2
/
I2C2
I2C1
CIF
MMC I/F
/
MMCI1
VIB_EN
GPIO
PA_MODE
PA_BAND
TXON_PA
PA_LEVEL
USIF2
I2S1
y
m
Gpu
{
l
y
m
h
j
l
Memory
FM_ANT
T
|
z
i
Gj
MUIC_DP/DM
VBUS_VCHG
DIF
/
DIF
Touch Sensor IC
SIM Socket
SIM I/F
SIM I/F
I2C1
/
I2C1
KEY_EN
GPIO
MUIC
MUIC_ID
I2C1
UART
HEADSET MIC
KEY Encoder
KEY_I2C
/
Vibrator
VIB_PWM
GPIO
I2C1
USB
/
CIF
I2C2
GPIO
Ear-jack
RF Transceiver(PMB6272)
Touch Window
Figure 1 GT350 Functional block diagram
ADC
ADC
Dig PGA
FEM Control
Bias DAC
DAC
÷4
÷2
÷4
÷2
Bias
A/AX
RX1/RX1X 850MHz
RX2/RX2X 900MHz
RX3/RX3X 1800MHz
RX4/RX4X 1900MHz
TX1
850/900MHz
TX2
1800/1900MHz
VBIAS
FE1
FE2
B/BX
EN DA CLK
26 MHz
FSYS1
X/XO
FSYS2
FSYS3
VCO_R
cordic I/Q => R/Φ
Sigma-Delta MASH Modulator
d/dt
2
2
2
PGA 1dB
Ramp
Integrated 3.8GHz VCO
26 MHz
.125dB
PGA 6dB
2
Q
I
OLG asjust
VCO control
fast CP
fast PFD
multi modulus divider
on chip loop filter
VCO-LDO
Timing & Measure ment
NI_NF
MOD
3-wire bus Sequencing
Содержание GT350
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