- 113 -
7. CIRCUIT DIAGRAM
LGE Internal Use Only
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
L
K
J
I
H
G
F
E
D
C
B
A
12
11
10
9
8
7
6
5
4
3
2
1
L
K
J
I
H
G
F
E
D
C
B
A
12
11
10
9
8
7
6
5
4
3
2
1
22p
C103
22p
C125
K0
1
00
1
R
00
1
PT
SD_1V8
TP101
00
1
C
u1
VIO_2V62
C101
39p
39p
C102
71
1
R
I
N
D
K2.
2
30
1
R
n0
1
93
1
C
32.768KHz
X100
FC-135
2
1
40
1
C
p9
3
VIO_2V62
50
1
C
u1.
0
60
1
C
u1.
0
p9
3
70
1
C
K0
01
20
1
R
VPLL_1V35
n0
1
80
1
C
u1.
0
01
1
C
11
1
C
u1.
0
21
1
C
u1.
0
RTC_2V11
VSIM_2V9
SD_1V8
u1
31
1
C
K7.
4
60
1
R
u1.
0
41
1
C
70
1
R
K2
2
n1
51
1
C
K0
01
80
1
R
K0
93
90
1
R
61
1
C
u2.
2
u1.
0
02
1
C
12
1
C
u1.
0
22
1
C
u1.
0
32
1
C
u1
CORE_1V35
VIO_2V62
VIO_2V62
42
1
C
u1.
0
UART100
12
11
10
9
8
7
6
5
4
3
2
1
GND
RX
TX
NC1
ON_SW
VBAT
NC2
NC3
NC4
DSR
RTS
CTS
GND
RX
TX
VCHAR
ON_SW
VBAT
PWR
URXD
UTXD
3G
2.5G
K1
01
1
R
VBAT
VBAT
50
1
PT
u1.
0
62
1
C
VAUDB_2V5
VAUDA_2V5
u1.
0
13
1
C
VMME_2V9
u1.
0
82
1
C
U100
PMB8877
6
E
1
K
4
H
4
E
2
E
3
E
4
1
F
6
1
G
6
1
J
9
1
H
4
F
1
E
3
F
5
F
5
1
F
9
1
C
3
1
Y
7
1
A
4
1
C
7
1
G
9
1
F
9
1
E
8
1
F
5
1
G
9
1
G
9
1
B
7
1
E
8
1
E
9
1
D
6
1
E
6
1
U
5
1
T
6
1
L
8
1
L
9
1
L
9
1
M
7
1
L
7
1
M
8
1
M
9
1
P
9
1
N
9
1
V
8
1
V
9
1
U
8
1
U
9
1
T
8
1
T
9
1
R
8
1
R
8
1
P
7
1
P
5
G
1
F
3
G
4
G
3
K
1
J
2
J
5
H
3
H
5
J
1
G
0
1
A
6
A
6
B
4
A
9
E
7
B
8
E
8
A
9
B
8
B
8
C
9
A
1
1
A
9
F
7
C
8
F
1
D
4
C
1
B
3
C
5
C
5
E
1
C
2
C
4
B
3
B
2
A
3
A
7
E
5
B
6
C
7
F
Y8
G18
T10
H17
Y9
J19
U11
J18
AA7
C10
R15
B16
R16
E14
Y14
H18
F16
W14
F13
AA15
C16
AA16
C15
B18
U10
A18
W8
Y7
G2
F2
Y4
U5
W11
V3
F6
AA2
D2
Y2
D3
Y3
A14
W3
F10
C9
R3
B11
L1
A12
M1
E10
K2
K17
T11
K18
H16
T5
T6
H15
U4
U12
U3
W12
N4
C18
N3
P3
B17
R2
E15
D18
P4
D17
M4
M5
R1
L4
K5
K4
J4
N2
C13
P2
B15
N1
B12
M3
C12
L5
E12
J3
C11
L3
B13
M2
F12
E11
T4
A15
T3
F11
P5
B14
T2
E13
R4
T1
K15
R5
M16
W2
M15
U2
N15
N5
M12
V1
K16
W9
U9
U15
Y6
Y16
W7
AA17
T9
W16
W6
Y17
AA5
AA18
Y5
W17
U7
Y18
T7
Y19
AA4
V17
W5
W18
U6
T8
W4
U8
2
1
Y
1
1
Y
5
1
Y
9
A
A
1
1
A
A
2
1
A
A
0
1
Y
8
A
A
7
1
N
8
1
N
7
1
U
9
1
W
7
1
R
7
1
T
5
1
J
6
1
N
6
1
P
4
1
U
3
1
T
5
1
W
3
1
U
4
1
T
6
1
T
5
1
L
5
1
P
2
L
2
1
T
3
1
W
4
1
A
A
3
1
A
A
9
1
K
3
1
A
0
1
B
1
H
7
1
J
2
H
7
A
2
B
7
1
C
6
1
A
5
A
7
1
F
0
1
W
1
W
2
V
1
U
1
P
1
Y
6
A
A
3
A
A
0
1
A
A
8
M
9
M
0
1
M
1
1
M
8
K
9
K
0
1
K
1
1
K
2
1
K
9
N
0
1
N
8
L
9
L
0
1
L
1
1
L
2
1
L
9
J
0
1
J
1
1
J
1
1
N
9
1
A
A
1
A
A
9
1
A
1
A
1
A_
R
E
N
R
O
C
2
A_
R
E
N
R
O
C
1
A
A_
R
E
N
R
O
C
2
A
A_
R
E
N
R
O
C
C
N
1
NI
A
M_
D
D
V
2
NI
A
M_
D
D
V
3
NI
A
M_
D
D
V
4
NI
A
M_
D
D
V
5
NI
A
M_
D
D
V
6
NI
A
M_
D
D
V
7
NI
A
M_
D
D
V
8
NI
A
M_
D
D
V
9
NI
A
M_
D
D
V
01
NI
A
M_
D
D
V
1
NI
A
M_
S
S
V
2
NI
A
M_
S
S
V
3
NI
A
M_
S
S
V
4
NI
A
M_
S
S
V
5
NI
A
M_
S
S
V
6
NI
A
M_
S
S
V
7
NI
A
M_
S
S
V
8
NI
A
M_
S
S
V
9
NI
A
M_
S
S
V
1
MT
E_
M
E
M_
P
D
D
V
2
MT
E_
M
E
M_
P
D
D
V
3
MT
E_
M
E
M_
P
D
D
V
4
MT
E_
M
E
M_
P
D
D
V
5
MT
E_
M
E
M_
P
D
D
V
1
MT
E_
M
E
M_
P
S
S
V
2
MT
E_
M
E
M_
P
S
S
V
3
MT
E_
M
E
M_
P
S
S
V
4
MT
E_
M
E
M_
P
S
S
V
A
GI
D_
P
D
D
V
B
GI
D_
P
D
D
V
1
C
GI
D_
P
D
D
V
2
C
GI
D_
P
D
D
V
D
GI
D_
P
D
D
V
2
GI
D_
P
S
S
V
1
GI
D_
P
S
S
V
3
GI
D_
P
S
S
V
E
GI
D_
P
D
D
V
4
GI
D_
P
S
S
V
C
M
M_
P
D
D
V
MI
S_
P
D
D
V
CT
R_
D
D
V
CT
R_
S
S
V
LL
P_
D
D
V
LL
P_
S
S
V
SF
_
E
S
UF
_
D
D
V
B
B_
A
D
D
V
B
B_
A
S
S
V
D_
A
D
D
V
D_
A
S
S
V
M_
A
D
D
V
M_
A
S
S
V
G
B_
A
D
D
V
G
B_
A
S
S
V
NF
E
R
V
D
N
G
A
D
R
A
U
G
1
R
B
V_
A
D
D
V
1
R
B
V_
A
S
S
V
2
R
B
V_
A
D
D
V
2
R
B
V_
A
S
S
V
T
B
V_
A
D
D
V
T
B
V_
A
S
S
V
0T
K
P
E
C
A
RT
1T
K
P
E
C
A
RT
2T
K
P
E
C
A
RT
3T
K
P
E
C
A
RT
4T
K
P
E
C
A
RT
5T
K
P
E
C
A
RT
6T
K
P
E
C
A
RT
7T
K
P
E
C
A
RT
MEM_A0
MEM_A1
MEM_A2
MEM_A3
M_0
MEM_A4
M_1
MEM_A5
M_2
MEM_A6
M_3
MEM_A7
M_4
MEM_A8
M_5
MEM_A9
M_6
MEM_A10
M_7
MEM_A11
M_8
MEM_A12
M_9
MEM_A13
M_10
MEM_A14
MEM_A15
PAOUT11
MEM_A16
PAOUT12
MEM_A17
BB_I
MEM_A18
BB_IX
MEM_A19
BB_Q
MEM_A20
BB_QX
MEM_A21
MEM_A22
T_OUT0
MEM_A23
T_OUT1
MEM_A24
T_OUT2
MEM_A25
T_OUT3
MEM_A26
T_OUT4
T_OUT5
MEM_AD0
T_OUT6
MEM_AD1
T_OUT7
MEM_AD2
T_OUT8
MEM_AD3
T_OUT9
MEM_AD4
T_OUT10
MEM_AD5
T_IN0
MEM_AD6
T_IN1
MEM_AD7
MEM_AD8
MEM_AD9
MEM_AD10
MEM_AD11
MEM_AD12
MEM_AD13
MEM_AD14
RF_STR0
MEM_AD15
RF_STR1
RF_DATA
MEM_CS0_N
RF_CLK
MEM_CS1_N
MEM_CS2_N
AFC
MEM_CS3_N
CLKOUT0
MEM_CSA0_N
F26M
MEM_CSA1_N
SWIF_TXRX
MEM_CSA2_N
MEM_CSA3_N
CC_IO
CC_CLK
FCDP_RBN
CC_RST
MEM_WAITN
MMCI1_CMD
MEM_ADVN
MMCI1_CLK
MEM_RDN
MMCI1_DAT0
MEM_WRN
MMCI1_DAT1
MMCI1_DAT2
MEM_BFCLKO1
MMCI1_DAT3
MEM_BFCLKO2
MMCI2_CMD
MEM_SDCLKO
MMCI2_DAT0
MEM_BC0_N
MMCI2_CLK
MEM_BC1_N
FWP
MEM_BC2_N
MEM_BC3_N
IRDA_TX
IRDA_RX
MEM_RAS_N
MEM_CAS_N
TDO
MEM_CKE
TDI
TMS
F32K
TCK
OSC32K
TRST_N
RESET_N
RTCK
RSTOUT_N
RTC_OUT
TRIG_IN
VREFP
MON1
IREF
MON2
TRACESYNC
SPCU_RQ_IN0
TRACECLK
SPCU_RQ_IN1
PIPESTAT2
SPCU_RC_OUT0
PIPESTAT1
SPCU_RQ_IN2
PIPESTAT0
0
D_
FI
D
1
D_
FI
D
2
D_
FI
D
3
D_
FI
D
4
D_
FI
D
5
D_
FI
D
6
D_
FI
D
7
D_
FI
D
8
D_
FI
D
1
S
C_
FI
D
2
S
C_
FI
D
D
C_
FI
D
R
W_
FI
D
D
R_
FI
D
D
H_
FI
D
D
V_
FI
D
1T
E
S
E
R_
FI
D
2T
E
S
E
R_
FI
D
0
D_
FI
C
1
D_
FI
C
2
D_
FI
C
3
D_
FI
C
4
D_
FI
C
5
D_
FI
C
6
D_
FI
C
7
D_
FI
C
KL
C
P_
FI
C
C
N
Y
S
H_
FI
C
C
N
Y
S
V_
FI
C
2T
U
O
KL
C
D
P_
FI
C
T
E
S
E
R_
FI
C
0
NI
_
P
K
1
NI
_
P
K
2
NI
_
P
K
3
NI
_
P
K
4
NI
_
P
K
5
NI
_
P
K
6
NI
_
P
K
0T
U
O_
P
K
1T
U
O_
P
K
2T
U
O_
P
K
3T
U
O_
P
K
11
N
P
E
21
N
P
E
11
P
P
E
21
P
P
E
11
A
P
P
E
21
A
P
P
E
1F
E
R
P
E
2F
E
R
P
E
12
A
P
P
E
22
A
P
P
E
1
N
CI
M
1
P
CI
M
2
N
CI
M
2
P
CI
M
1
N
X
U
A
1
P
X
U
A
2
N
X
U
A
2
P
X
U
A
D
N
G
X
U
A
P
CI
M
V
N
CI
M
V
0
KL
C_
1
S2I
1
KL
C_
1
S2I
X
R_
1
S2I
XT
_1
S2I
0
A
W_
1
S2I
0
KL
C_
2
S2I
1
KL
C_
2
S2I
X
R_
2
S2I
XT
_2
S2I
0
A
W_
2
S2I
1
A
W_
2
S2I
L
C
S_
1
C2I
A
D
S_
1
C2I
T
NI
_
M
P
L
C
S_
2
C2I
A
D
S_
2
C2I
T
S
R
M_
D
X
R_
1FI
S
U
R
ST
M_
D
XT
_1
FI
S
U
N_
ST
R_
1FI
S
U
N_
ST
C_
1FI
S
U
T
S
R
M_
D
X
R_
2FI
S
U
R
ST
M_
D
XT
_2
FI
S
U
N_
ST
R_
2FI
S
U
N_
ST
C_
2FI
S
U
T
S
R
M_
D
X
R_
3FI
S
U
R
ST
M_
D
XT
_3
FI
S
U
KL
C
S_
3FI
S
U
0
NI
P
S
D
1
NI
P
S
D
1T
U
O
P
S
D
K1
11
1
R
TP110
u1.
0
03
1
C
11
1
PT
u1.
0
23
1
C
u1.
0
33
1
C
C134
220n
K2.
2
10
1
R
u1.
0
83
1
C
V_BUS
41
1
R
K7.
4
R119
DNI
n0
1
53
1
C
04
1
C
n0
1
n0
1
44
1
C
64
1
C
n0
1
K3.
3
50
1
R
TP103
u1.
0
91
1
C
71
1
C
u2.
2
SD_1V8
40
1
R
K0
1
0
61
1
R
u1.
0
90
1
C
92
1
C
u1.
0
SD_1V8
SD_1V8
TP106
TP108
TP109
K0
01
81
1
R
TP112
TP104
81
1
C
n0
1
u1.
0
14
1
C
54
1
C
u1.
0
63
1
C
u1.
0
n0
1
73
1
C
1u
C142
1u
C143
u1.
0
72
1
C
0
51
1
R
TP115
TP116
TP117
VIO_2V62
K522H1HACB-B060
U101
21
T
11
T
01
T
3T
2T
1T
21
R
11
R
01
R
3
R
2
R
1
R
21
P
11
P
3
P
2
P
1
P
2
N
2
M
2L
01
K
9
K
8
K
5
K
4
K
2
K
11
J
01
J
9J
8J
7J
6J
5J
4J
3J
P8
D5
P4
D6
E6
P6
F6
C8
F5
C4
E5
D7
P5
C7
C6
P9
L7
P7
L6
H10
K7
G2
K6
C9
N9
C5
M9
L9
H2
N8
M8
N3
L8
E3
N7
K3
M7
L3
N6
F3
M6
M3
N5
G3
M5
L5
D11
N4
E11
M4
F11
L4
G11
E9
K11
E7
L11
F7
M11
G5
N11
G7
C10
D9
D10
D8
E10
E8
F10
F8
L10
G8
M10
G4
N10
F4
P10
E4
D4
2J
9
H
8
H
7
H
6
H
5
H
4
H
3
H
01
G
9
G
6
G
9F
2F
11
H
2
E
3
D
2
D
1
D
21
C
11
C
3
C
2
C
1
C
21
B
11
B
01
B
3
B
2
B
1
B
21
A
11
A
01
A
3
A
2
A
1
A
1
C
N
2
C
N
3
C
N
4
C
N
5
C
N
6
C
N
7
C
N
8
C
N
9
C
N
01
C
N
11
C
N
21
C
N
31
C
N
41
C
N
51
C
N
61
C
N
71
C
N
81
C
N
91
C
N
02
C
N
12
C
N
22
C
N
32
C
N
42
C
N
52
C
N
62
C
N
72
C
N
82
C
N
92
C
N
03
C
N
13
C
N
23
C
N
33
C
N
43
C
N
53
C
N
A0
A1
I_O0
A2
I_O1
A3
I_O2
A4
I_O3
A5
I_O4
A6
I_O5
A7
I_O6
A8
I_O7
A9
I_O8
A10
I_O9
A11
I_O10
A12
I_O11
A13
I_O12
DQ0
I_O13
DQ1
I_O14
DQ2
I_O15
DQ3
DQ4
_CE
DQ5
_WEN
DQ6
_RE
DQ7
ALE
DQ8
CLE
DQ9
R__B
DQ10
_WP
DQ11
DQ12
VCCN1
DQ13
DQ14
VSS1
DQ15
VSS2
LDQM
VSS3
UDQM
VSS4
LDQS
VSS5
UDQS
VSS6
_CLK
CLK
VSSQ
CKE
BA0
VDD1
BA1
VDD2
_RAS
VDD3
_CAS
_WED
VDDQ1
_CS
VDDQ2
63
C
N
73
C
N
83
C
N
93
C
N
04
C
N
14
C
N
24
C
N
34
C
N
44
C
N
54
C
N
64
C
N
74
C
N
84
C
N
94
C
N
05
C
N
15
C
N
25
C
N
35
C
N
45
C
N
55
C
N
65
C
N
75
C
N
85
C
N
95
C
N
06
C
N
16
C
N
26
C
N
36
C
N
46
C
N
56
C
N
66
C
N
76
C
N
86
C
N
96
C
N
07
C
N
TP102
TP107
T
NI
_
W
S
U
_CHG_EOC
LCD_BACKLIGHT_EN
ADD[29]
ADD[29]
BAT_ID
VIB_PWM
]2[
T
U
O_
P
K
T
NI
_
H
C
U
OT
N
E_
O
DL
_
M
A
C
DATA[10]
DATA[10]
DATA[15]
DATA[15]
DATA[13]
DATA[13]
DATA[12]
DATA[12]
DATA[11]
DATA[11]
DATA[9]
DATA[9]
DATA[8]
DATA[8]
DATA[2]
DATA[2]
DATA[7]
DATA[7]
DATA[6]
DATA[6]
DATA[5]
DATA[5]
DATA[4]
DATA[4]
DATA[3]
DATA[3]
DATA[1]
DATA[1]
DATA[0]
DATA[0]
T
E
D_
C
M
M
]5[
NI
_
P
K
R_
D
N
S_
B
B
L_
D
N
S_
B
B
EAR_P
EAR_N
PA_LEVEL
UDQS
UDQS
LDQS
LDQS
ADD[28]
ADD[28]
ADD[27]
ADD[27]
ADD[26]
ADD[26]
E
D
O
M_
FI
A
D
S_
2
C2I
L
C
S_
2
C2I
KL
C
M_
FI
C
M
V_
0
E
S_
B
S
U
VIB_EN
MMC_DATA[3]
MMC_DATA[0]
MMC_CMD
MMC_CLK
SDCLKI
SDCLKI
N
E_
Y
E
K
G
O
D
W
RPWRON
]3[
T
U
O_
P
K
]0[
T
U
O_
P
K
]3[
NI
_
P
K
DI
_
D
CL
USB_OEN
T
E
S
E
R_
FI
C
D
P_
FI
C
KL
C
P_
FI
C
C
N
Y
S
H_
FI
C
]6[
NI
_
P
K
_PPR
K2
3
KL
C
_CHG_EN
C
N
Y
S
V_
FI
D
NF
E
R
V
VREFN
P_
CI
M
V
N_
CI
M
V
N
E_
O
X
C
V
MMC_DATA[1]
MMC_DATA[2]
JACK_DETECT
PA_MODE
PA_BAND
TXON_PA
A
D
S_
C2I
L
C
S_
C2I
RTC_OUT
RF_EN
RF_DA
RF_CLK
_RESET
P_
CI
M_
S
H
P_
CI
M_
NI
A
M
N_
CI
M_
S
H
N_
CI
M_
NI
A
M
RF_TEMP
26MHZ_MCLK
_WR
_WR
_WR
SDCLKO
SDCLKO
_RD
_RD
_RAM_CS
_RAM_CS
CKE
CKE
_CAS
_CAS
FCDP
FCDP
_BC1
_BC1
_BC0
_BC0
_NAND_CS
_NAND_CS
ADD[25]
ADD[25]
ADD[4]
ADD[4]
ADD[3]
ADD[3]
ADD[24]
ADD[24]
ADD[23]
ADD[23]
ADD[22]
ADD[22]
ADD[21]
ADD[21]
ADD[20]
ADD[20]
ADD[2]
ADD[2]
ADD[19]
ADD[19]
ADD[18]
ADD[18]
ADD[17]
ADD[17]
ADD[17]
ADD[16]
ADD[16]
ADD[16]
ADD[9]
ADD[9]
ADD[8]
ADD[8]
ADD[13]
ADD[13]
ADD[7]
ADD[7]
ADD[12]
ADD[12]
ADD[6]
ADD[6]
ADD[11]
ADD[11]
ADD[5]
ADD[5]
ADD[10]
ADD[10]
ADD[1]
ADD[1]
ADD[0]
ADD[0]
P
V_
T
A
D_
B
S
U
R
W_
FI
D
T
E
S
E
R_
FI
D
7
D_
FI
D
6
D_
FI
D
5
D_
FI
D
4
D_
FI
D
3
D_
FI
D
2
D_
FI
D
1
D_
FI
D
0
D_
FI
D
S
C_
FI
D
D
C_
FI
D
D
R_
FI
D
T
C
ET
E
D_
K
O
O
H
7
D_
FI
C
6
D_
FI
C
5
D_
FI
C
4
D_
FI
C
3
D_
FI
C
2
D_
FI
C
1
D_
FI
C
0
D_
FI
C
SIM_RST
SIM_IO
SIM_CLK
QX
Q
IX
I
_RAS
_RAS
L
RT
C_
E
C
R
U
O
S
E
R
USB_DP
USB_DM
DSR
DSR
UART_TX
UART_TX
XT
_T
R
A
U
UART_RX
UART_RX
X
R_
T
R
A
U
RPWRON_EN
RPWRON_EN
T
NI
_
M
P
ADD[15]
ADD[15]
ADD[14]
ADD[14]
DATA[14]
DATA[14]
KL
C_
2
S2I
O
D
S_
2
S2I
S
W_
2
S2I
FM_SPK_INN
FM_SPK_INP
X
R_
T
R
A
U_
T
B
N_
T
E
S
E
R_
T
B
XT
_T
R
A
U_
T
B
KL
C_
M
C
P_
T
B
NI
_
M
C
P_
T
B
T
U
O_
M
C
P_
T
B
C
N
Y
S_
M
C
P_
T
B
BA0
BA0
BA1
BA1
_WP
_WP
ST
C_
T
R
A
U_
T
B
ST
R_
T
R
A
U_
T
B
P
U
E
K
A
W_
T
S
O
H_
T
B
FM_LNA_CTRL
RCV_FM_SEL
D
N
G
_
C
I
M
C
N
Y
S
V_
FI
C
DATA[0:15]
ADD[0:26]
ADD[16:29]
ADD[0:15]
DATA[0:15]
MUIC
TOUCH
I2C2_SDA
I2C2_SCL
I2C_SDA
For product inspection TP
10 GND
8 GND
AUDIO AMP
TRACE32(20 Pin)
I2C2
I2C1
10 GND
PIN NET
6 GND
4 GND
3 JTAGEN
1 2V8
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
J-TAG
Large Block Memory
P/U 1K
14 GND
20 GND
18 GND
16 GND
12 GND
19
17
11
4 GND
13 TDO(DBB Out)
9 TCK
2
8 GND
Small Block
Large Block
PIN NET
)
%1(
)
%1(
100K
* Model check
PMIC
2 GND
13 2V8
9 TCK
I2C_SCL
CAMERA
VALUE
PIN NET
GS290
TRIG_IN
GS390
DNI
11 TDO(DBB out)
14 GND
7 TMS
5 TDI
12 _RESET
PIN NET
6 GND
7 TMS
5 TDI
15 _RESET
3 JTAGEN
1 2V8
TRACE32(14 Pin)
* Boot Mode
BASE BAND PROCESSOR
P/D 10K